VerilogHDL硬件驅(qū)動(dòng)電路設(shè)計(jì)湖北師范學(xué)院田開坤2014.10課堂練習(xí)分頻電路10Hz3bits

計(jì)數(shù)器38

譯碼器數(shù)據(jù)

比較器50M3clk_10Hz.v(clk,clr,clko)cnt_3bits.v(clk,clr,q)ym_38.v(a,y)bj.v(a,y)moduletop(clk,clr,[7:0]y,out);wireckinside;wire[2:0]cnt_d;clk_10HzAA(.clk(clk),.clr(clr),.clko(ckinside));cnt_3bitsBB(.clk(ckinside),.clr(clr),.q(cnt_d));ym_38CC(.a(cnt_d),.y(y));bjDD(.a(cnt_d),.y(out));endmoduleckinsidecnt_d50M-10Hz分頻電路，5Minputclk,clr;outputclko;reg[21:0]counter;regclko;always@(posedgeclkornegedgeclr)begin if(counter<5M/2-1)counter=coutnter+1; elsebegincounter=0;clko=!clko;endend3bits計(jì)數(shù)器inputclk,clr;output[2:0]q;reg[2:0]q;always@(posedgeclkornegedgeclr)if(!clr)q=0;elseq=q+1;3bits比較器input[2:0]a;outputy;wirey;assigny=(a<3’H3)?1:0;38譯碼器input[2:0]a;output[7:0]y;always@(a)begincase(a)0:y=8'b00000001;1:y=8'b00000010;2:y=8'b00000100;3:y=8'b00001000;4:y=8'b00010000;5:y=8'b00100000;6:y=8'b01000000;

default:y=8'b10000000;endcaseend數(shù)碼管驅(qū)動(dòng)電路關(guān)于數(shù)碼管關(guān)于數(shù)碼管CLK計(jì)數(shù)器LED燈驅(qū)動(dòng)一只共陰極7段數(shù)碼管循環(huán)顯示0~98FPGA時(shí)鐘計(jì)數(shù)器字符譯碼分頻器div_clk.v(clk,clko)cnt9.v(clk,q)deled.v(d,y)inputclk_50m;output[6:0]y;wireclk_1hz;wire[3:0]num;div_clkAA(.clk(clk_50m),.clko(clk_1hz));cnt9BB(.clk(clk_1hz),.q(num));deledCC(.d(num),.y(y));字符譯碼電路input[3:0]d;output[6:0]y;wire[6:0]y;assigny=(d==0)?“0”:(d==1)?”1”:”2”:…:(d==9)?”9”:7’b000_0000;0~9計(jì)數(shù)器電路inputclk;output[3:0]q;reg[3:0]q;always@(posedgeclk)beginif(q<9)q=q+1;elseq=0;end分頻器電路:50Mhzinputclk;outputclko;regclko;reg[n:0]cnt;always@(posedgeclk)beginif(cnt<??)cnt=cnt+1;elsebegincnt=0;clko=!clko;endend數(shù)碼管顯示的計(jì)數(shù)器結(jié)構(gòu)框圖8字符

譯碼數(shù)據(jù)input[3:0]d;outputa,b,c,d,e,f,g,p;always@(d)begincase(d)

0:{a,b,c,d,e,f,g,p}=8’HFC;1:{a,b,c,d,e,f,g,p}=8’H60;2:{a,b,c,d,e,f,g,p}=8’HFA;...

default:{a,b,c,d,e,f,g,p}=8‘H00;endcaseend數(shù)碼管顯示的計(jì)數(shù)器結(jié)構(gòu)框圖8字符

譯碼數(shù)據(jù)8…驅(qū)動(dòng)器(145)3bits計(jì)數(shù)器數(shù)據(jù)選擇器時(shí)

鐘分頻50M數(shù)碼管顯示的計(jì)數(shù)器結(jié)構(gòu)框圖8字符

譯碼8…驅(qū)動(dòng)器(145)掃描驅(qū)動(dòng)電路數(shù)據(jù)選擇器0~9計(jì)數(shù)器0~9計(jì)數(shù)器…1Hz數(shù)碼管顯示的計(jì)數(shù)器結(jié)構(gòu)框圖數(shù)碼管

驅(qū)動(dòng)電路0~9計(jì)數(shù)器0~9計(jì)數(shù)器……1Hz8.8...850M分頻器inputclk,clr;output[3:0]q,c;always@(…)if(q<9)beginq=q+1;c=0;endelsebeginq=0;c=1;end數(shù)據(jù)選擇器input[2:0]sel;output[3:0]d;assignd=(sel==3’H0)?2:(sel==3’H1)?0:(sel==3’H2)?1:…4:…1:…0:…2:7;7段LED字符譯碼器7段LED字符譯碼器moduledeled(num,a,b,c,d,e,f,g);input[3:0]num;outputa,b,c,d,e,f,g;assign{a,b,c,d,e,f,g}=(num==0)?7’b#######:(num==1)?7’b#######:……7’b########;endmodule7段LED字符譯碼器reg

a,b,c,d,e,f,g;always@(num)begin

case(num) 0:{a,b,c,d,e,f,g}=7’b########;1:{a,b,c,d,e,f,g}=7’b########;……

default:{a,b,c,d,e,f,g}=7’b0000000;endendmodule7段LED字符譯碼器moduledeled(D,a,b,c,d,e,f,g);input[3:0]D;outputa,b,c,d,e,f,g;assign{a,b,c,d,e,f,g}=(D==0)?#######: (D==1)?#######: ………. (D==9)?#######;endmodule7段LED字符譯碼器reg

a,b,c,d,e,f,g;always@(D)begincase(D)1:{a,b,c,d,e,f,g}=7’b011000000;2:{a,b,c,d,e,f,g}=7’b#######;……7:{a,b,c,d,e,f,g}=7’b#######;

default:{a,b,c,d,e,f,g}=7’b0000000;

endcaseend0～9計(jì)數(shù)器進(jìn)位允許進(jìn)位允許進(jìn)位允許0～9計(jì)數(shù)器0～9計(jì)數(shù)器0～9計(jì)數(shù)器數(shù)據(jù)

選擇器數(shù)碼管

單元電路計(jì)數(shù)時(shí)鐘掃描時(shí)鐘字符譯碼掃描計(jì)數(shù)器A[3..0]B[3..0]C[3..0]D[3..0]Q[3..0]SEL[1..0]a,b,c,d,e,f,g9999計(jì)數(shù)器0～9計(jì)數(shù)器進(jìn)位允許進(jìn)位允許進(jìn)位允許0～9計(jì)數(shù)器0～9計(jì)數(shù)器0～9計(jì)數(shù)器數(shù)據(jù)

選擇器數(shù)碼管

單元電路計(jì)數(shù)時(shí)鐘掃描時(shí)鐘字符譯碼掃描計(jì)數(shù)器A[3..0]B[3..0]C[3..0]D[3..0]Q[3..0]SEL[1..0]a,b,c,d,e,f,g9999計(jì)數(shù)器多位數(shù)碼管并聯(lián)驅(qū)動(dòng)moduletop(clk,clr,d,s);inputclk,clr;output[6:0]d;output[1:0]s;wire[3:0]num;wirek0;mux41MA(.A(1),.B(2),.C(3),.D(4),.Q(num),.S(s));deledDB(.num(num),.d(d));c_scanSC(.clk(ck0),.q(s));div_clkCD(.clk(clk),.clr(clr),.k0(k0));endmodule數(shù)碼管掃描驅(qū)動(dòng)電路時(shí)鐘十進(jìn)制計(jì)數(shù)器十進(jìn)制計(jì)數(shù)器數(shù)據(jù)選擇器掃描計(jì)數(shù)器時(shí)鐘2數(shù)碼管電路數(shù)碼管顯示計(jì)數(shù)器完整框圖復(fù)位字符譯碼器按鍵輸入一般邏輯輸入帶鎖存狀態(tài)輸入時(shí)鐘輸入復(fù)位輸入按鍵——多功能計(jì)數(shù)器設(shè)計(jì)通過(guò)一個(gè)按鍵選擇計(jì)數(shù)模式按鍵一次，計(jì)數(shù)模式切換一次加減計(jì)數(shù)器時(shí)鐘復(fù)位模式選擇Q[7:0]modulecounter(clk,clr,ms,q);inputclk,clr,ms;output[7:0]q;reg[7:0]q;regstate;always@(posedgemsornegedge

clr)

if(!clr)state=0; elsestate=!state;always@(posedge

clkornegedge

clr)begin

if(!clr)q=0; elsebegin

if(state)q=q+1; elseq=q-1; endendendmoduleLED驅(qū)動(dòng)一般電平驅(qū)動(dòng)亮度調(diào)整花樣燈蜂鳴