XilinxXilinx1、打開Vivado2015.4,“CreateNewProject”,3“Next”,“Create4“Next”,“RTLProject”5“Next”7“Next”Summary8“Finish”9“FlowNavigator”“ProjectManager”“AddSources”,在彈出的窗口中選擇“Addorcreatedesignsources”。10“Next”,“CreateFile”,“counter”11“OK”,“Finish”12“OK”,“Yes”13“Sources”“DesignSources”“counter.v”16“FlowNavigator”“ProjectManager”“AddSources”,在彈出的窗口中選擇“Addorcreatesimulationsources”,點(diǎn)擊“Next”。17“CreateFile”,18“OK”,“Finish”19“OK”,“Yes”20“Sources”“SimulationSources”,21“FlowNavigator”“Simulation”“RunSimulation”,247ms“Break”“ZoomFit”,將6ms“OK”,關(guān)閉仿真界面。25“FlowNavigator”“Synthesis”“RunSynthesis”。右上角的進(jìn)度條“Runningsynth_design”指示正在對(duì)工程進(jìn)行綜合。26“OpenSynthesizedDesign”,“OK”,打27“I/OPorts”“I/OStd”一欄通過下拉按鈕選擇“LVCOMS33”,3.3V。28“Site”FPGA30“FileName”“flash_led_top”,31“OK”“SynthesizedDesign”32、在“Sources”窗口中的“Constraints/constrs_1”下雙擊“flash_led_top.xdc”,打開33“SynthesisOut-of-date提示需要重新進(jìn)行綜合。在“FlowNavigator”一欄中的“Synthesis”下點(diǎn)擊“RunSynthesis”。34“RunImplementation”,“OK”,進(jìn)入實(shí)“Cancel”“FlowNavigator”“Implementation”下點(diǎn)擊“RunImplementation”。bit35“GenerateBitstream”,“OK”。這一過FPGA。“Cancel”“FlowNavigator”“ProgramandDebug”下點(diǎn)擊“GenerateBitstream”。36“OpenHardwareManager”“OK”37MicroUSBJTAG“HardwareManager”界面點(diǎn)擊“Opentarget”,選擇“AutoConnec