1、簡單計算器設(shè)計EDA實驗報告一、實驗內(nèi)容實驗要求：完成個位數(shù)的加減乘運(yùn)算，輸入用矩陣鍵盤，輸出用數(shù)碼管顯示，每輸入一次數(shù)據(jù)要顯示在數(shù)碼管上。矩陣鍵盤共16個按鍵，用其中10個做個位數(shù)的輸入，用3個分別做加減乘運(yùn)算，用其中1個做等于操作，各位數(shù)的運(yùn)算結(jié)果最多兩位，用動向掃描數(shù)碼管顯示運(yùn)算結(jié)果。二、小組成員三、實現(xiàn)方法系統(tǒng)組成及連結(jié)原理以下列圖，主要由由七個功能模塊組成：分頻模塊（為鍵盤掃描模塊和防抖模塊供應(yīng)時鐘）、鍵盤掃描驅(qū)動模塊（依次置零）、鍵盤按鍵值編碼模塊、鍵盤編碼值防抖模塊、運(yùn)算模塊，數(shù)碼管顯示驅(qū)動模塊、動向掃描驅(qū)動模塊。行鍵時值分鍵盤矩陣鐘驅(qū)防抖頻編動碼數(shù)碼管顯運(yùn)算數(shù)碼管動向顯示1.分

2、頻模塊由于FPGA實驗板的原始時鐘頻率高達(dá)33.8688MHz，所以不能夠直接接入設(shè)計模塊中使用，就需要用到分頻模塊。將33.8688MHz分頻到4KHz和10Hz來使用，一個用于行驅(qū)動掃描時鐘，一個用于防抖模塊。所以，采用寫一個可變分頻元件來調(diào)用。元件視圖：主要代碼以下（完滿代碼見附錄，下同）：architectureRTLoffreq_divisioniscomponentfredivnisgeneric(n:positive);Port(clkin:inSTD_LOGIC;clkout:outSTD_LOGIC);endcomponent;beginU1:fredivngenericma

3、p(n=3)portmap(clkin=clk,clkout=clkout_kb);endRTL;仿真結(jié)果以以下列圖：達(dá)到預(yù)期的目的2.行驅(qū)動模塊（依次對行置零）：鍵盤掃描的原理就是檢測行列信號爾后判斷出詳盡是按下了哪一個按鍵。所以，對行依次置零，當(dāng)置零頻率較快時，按下某一個按鍵后，必然能獲取某一列的信號輸出為零，以以下列圖：當(dāng)行信號為1110時，若按下了0鍵，就會獲取1110的列信號，立馬就快能夠譯碼出按鍵值，若按下4鍵、8鍵、C鍵則都不會有輸出。主要代碼以下：process(clkin)beginifclr=1thencount=00;elsifrising_edge(clkin)then

4、ifcount=11thencount=00;elsecount=count+1;endif;endif;endprocess;process(count)beginifcount=01thenelsifcount=10thenelsifcount=11thenelsifcount=00thenendif;keydrv=1110;keydrv=1101;keydrv=1011;keydrv=0111;endprocess;仿真結(jié)果以以下列圖：達(dá)到預(yù)期的目的3.鍵值編碼模塊依照行驅(qū)動模塊，當(dāng)按下某一個按鍵后，立馬能夠依照行列和并位信號獲取唯一的鍵盤編碼值，用5位矢量來保存結(jié)果，當(dāng)沒有按鍵按下時，

5、編碼值素來保持著11111不變，并在后端的模塊中不對其做任何辦理。以以下出部分編碼表（完滿編碼表見附錄）：十進(jìn)制數(shù)行&列HEX七段碼HEX0EE7E4DE335DD5B主要代碼以下：process(clk)beginifclr=0thenifrising_edge(clk)theniftemp1=11101110thenkeyvalue1=00000;-0elsiftemp1=11101101thenkeyvalue1=00001;-1elsiftemp1=11101011thenkeyvalue1=00010;-2elsiftemp1=11100111thenkeyvalue1=00011;

6、-3elsiftemp1=11011110thenkeyvalue1=00100;-4elsiftemp1=11011101thenkeyvalue1=00101;-5elsiftemp1=11011011thenkeyvalue1=00110;-6elsiftemp1=11010111thenkeyvalue1=00111;-7elsiftemp1=10111110thenkeyvalue1=01000;-8elsiftemp1=10111101thenkeyvalue1=01001;-9elsiftemp1=10111011thenkeyvalue1=01010;-10elsiftemp1

7、=10110111thenkeyvalue1=01011;-11elsiftemp1=01111110thenkeyvalue1=01100;-12elsiftemp1=01111101thenkeyvalue1=01101;-13elsiftemp1=01111011thenkeyvalue1=01110;-14elsiftemp1=01110111thenkeyvalue1test1test2test3test4test5test6test7test8test9test10test11test12test13test14test15test16null;endcase;iftest1=te

8、st5andtest2=test6andtest3=test7andtest4=test8andtest5=test9andtest6=test10andtest7=test11andtest8=test12andtest9=test13andtest10=test14andtest11=test15andtest12=test16andtest1/=UUUUUUUUthen仿真波形以下：從圖中能夠看出最后temp1從臨時信號temp獲取最后輸出，達(dá)到防抖：5.運(yùn)算模塊當(dāng)前段的模塊經(jīng)過防抖辦理今后獲取牢固的按鍵信號，比方1+2=3,轉(zhuǎn)變成編碼值就是主要代碼以下：ifysfh=0thenresu

9、lt=first+second;elsifysfh=1thenresult=first-second;elsifysfh=2thenresult=first*second;endif;n=n+1;elsifn=100thenn=000;endif;endif;endprocess;process(n)beginifn=001thenkeyvaluein=conv_std_logic_vector(first,8);elsifn=011thenkeyvaluein=conv_std_logic_vector(second,8);elsifn=100thenkeyvaluein=conv_std_

10、logic_vector(result,8);endif;endprocess;仿真波形以下：以1+3=4和5x6=30為例：編碼：01+03=0405X06=1E6.數(shù)碼管顯示模塊以及動向掃描模塊由于次兩個模塊是親近相關(guān)的，所以一致到一起考據(jù)。經(jīng)過運(yùn)算獲取最后的顯示結(jié)果后，要在七段數(shù)碼管中顯示，就必定有每一個數(shù)的七段碼，同時，由于前面的運(yùn)算模塊的結(jié)果最大能夠達(dá)到81，也就是需要8位二進(jìn)制，兩位十進(jìn)制來表示，所以就必定經(jīng)過顯示模塊來分別出十位和個位。分別出十位和個位今后，就必定要利用動向掃描使兩個數(shù)都能顯示出來。由于段數(shù)碼管的abcdefg位是連在一起的，只有利用分時間隔來顯示，一次使能一個數(shù)

11、碼管，顯示一位數(shù)，當(dāng)頻率較高時，就可以獲取兩位數(shù)的顯示收效。8個七數(shù)碼管顯示模塊主要代碼以下：ifnum=0thenten:=0;one:=10;elsifnum0thenten:=0;one:=num;elsifnum9thenten:=1;one:=num-10;elsifnum19thenten:=2;one:=num-20;elsifnum29thenten:=3;one:=num-30;elsifnum39thenten:=4;one:=num-40;elsifnum49thenten:=5;one:=num-50;elsifnum59thenten:=6;one:=num-60;e

12、lsifnum69thenten:=7;one:=num-70;elsifnum79thenten:=8;one:=num-80;elsifnum89thenten:=9;one:=num-90;endif;t=conv_std_logic_vector(ten,4);o=conv_std_logic_vector(one,4);動向掃描模塊主要代碼以下：ifcount=00thenshowout=show1;en=00000010;elsifcount=01thenshowout=show2;enshowout01100003002=showout11011016D03=showout111

13、100179由以上波形能夠看出：01+02=03的計算完成了。五、總結(jié)本次EDA設(shè)計實踐，完成了從VHDL代碼編寫到硬件實現(xiàn)的整個流程，掌握了一些FPGA的相關(guān)看法以及ISE軟件和Active-HDL軟件的使用方法。最重要的就是組員之間的合作，由于VHDL程序是模塊化編寫的，所以不同樣模塊是由不同樣人來完成編譯的，要達(dá)到各個模塊之間能夠優(yōu)異的連結(jié)通信，就必定有一個很好的溝通溝通，把大家的思路集中起來，一起談?wù)摗⒕帉?、調(diào)試程序。【附錄一】完滿程序：分頻：libraryIEEE;useIEEE.STD_LOGIC_1164.ALL;useIEEE.STD_LOGIC_ARITH.ALL;useIE

14、EE.STD_LOGIC_UNSIGNED.ALL;entityfredivnisgeneric(n:integer:=3);Port(clkin:inSTD_LOGIC;clkout:outSTD_LOGIC);endfredivn;architectureBehavioraloffredivnissignalclk1:std_logic:=0;signalcounter:integerrange0ton;beginprocess(clkin)beginifrising_edge(clkin)thenifcounter=(n-1)/2thenclk1=notclk1;counter=0;el

15、secounter=counter+1;endif;endif;endprocess;libraryIEEE;useIEEE.STD_LOGIC_1164.ALL;useIEEE.STD_LOGIC_ARITH.ALL;useIEEE.STD_LOGIC_UNSIGNED.ALL;entitykeyscanisPort(clr:instd_logic;clkin:inSTD_LOGIC;keydrv:outSTD_LOGIC_VECTOR(3downto0);endkeyscan;architecturebehavioralofkeyscanissignalcount:std_logic_ve

16、ctor(1downto0);beginprocess(clkin)beginifclr=1thencount=00;elsifrising_edge(clkin)thenifcount=11thencount=00;elsecount=count+1;endif;endif;endprocess;process(count)beginifcount=01thenkeydrv=1110;elsifcount=10thenkeydrv=1101;clkout=clk1;elsifcount=11thenendBehavioral;keydrv=1011;elsifcount=00thenkeyd

17、rvclkin,keydrv=keydrv1,clr=clr);tempclkin,temp=temp,key1temp1,clr=clr);key2=00001;process(clk)key3=00010;beginkey4=00011;ifclr=0thenkey5=00100;ifrising_edge(clk)thenkey6=00101;iftemp1=11101110key7=00110;thenkeyvalue1=00000;key8=00111;elsiftemp1=11101101thencount1=000;keyvalue1=00001;start_1=1;elsift

18、emp1=11101011elsethenkeyvalue1=00010;ifrising_edge(clk_f)thenelsiftemp1=11100111ifcount1=111thenthenkeyvalue1=00011;count1=000;elsiftemp1=11011110elsecount1=count1+1;thenkeyvalue1=00100;endif;elsiftemp1=11011101endif;thenkeyvalue1=00101;endif;elsiftemp1=11011011casecount1isthenkeyvalue1key1key2=keyc

19、ode;thenkeyvalue1key3key4=keycode;thenkeyvalue1key5key6=keycode;thenkeyvalue1key7key8=keycode;thenkeyvalue1null;elsiftemp1=10110111endcase;thenkeyvalue1=01011;ifkey1=key2andkey2=key3andelsiftemp1=01111110key3=key4andkey4=key5andthenkeyvalue1=01100;key5=key6andkey6=key7andelsiftemp1=01111101key7=key8

20、andkey1/=UUUUUthenthenkeyvalue1=01101;elsiftemp1=01111011keycode1=key1;start_1=0thenkeyvalue1=01110;after5ns;elsiftemp1=01110111endif;thenkeyvalue1=01111;endprocess;endif;start=start_1;endif;endfangdou;endif;endprocess;keycode=keyvalue1;endrtl;運(yùn)算：數(shù)碼管顯示：libraryIEEE;libraryIEEE;useIEEE.STD_LOGIC_1164.

21、ALL;useIEEE.STD_LOGIC_1164.all;useIEEE.STD_LOGIC_ARITH.ALL;useieee.std_logic_arith.all;useIEEE.STD_LOGIC_UNSIGNED.ALL;useieee.std_logic_unsigned.all;useieee.numeric_std.all;entityshumaguanxianshiisentityyunsuanisport(keyvaluein:inport(start:instd_logic;std_logic_vector(7downto0);keycode1:instd_logic

22、_vector(4downto0);clk:instd_logic;keyvaluein:outstd_logic_vector(7downto0);show1,show2:outendyunsuan;std_logic_vector(6downto0);architectureBehavioralofyunsuanisendshumaguanxianshi;signalfirst,second,result,ysfh:integerarchitectureshumaguanxianshirange0to99;ofshumaguanxianshiissignaln:std_logic_vect

23、or(2downto0);signalt:std_logic_vector(3begindownto0);process(start,keycode1)signalo:std_logic_vector(3begindownto0);ifstart=1thenbeginn=000;process(clk)elseifn=000thenvariablenum:integerrange0to99;ifkeycode1=00001thenfirst=1;variableten,one:integerrange0toelsifkeycode1=00010then15;first=2;beginelsif

24、keycode1=00011thenfirst=3;ifrising_edge(clk)thenelsifkeycode1=00100thenfirst=4;num:=conv_integer(keyvaluein);elsifkeycode1=00101thenfirst=5;ifnum=0thenelsifkeycode1=00110thenfirst=6;elsifkeycode1=00111thenfirst=7;elsifkeycode1=01000thenfirst=8;elsifkeycode1=01001thenfirst=9;elsifkeycode1=00000thenfi

25、rst=0;endif;n=n+1;elsifn=001thenifkeycode1=01010thenysfh=0;elsifkeycode1=01011thenysfh=1;elsifkeycode1=01100thenysfh=2;endif;n=n+1;elsifn=010thenifkeycode1=00001thensecond=1;elsifkeycode1=00010thensecond=2;elsifkeycode1=00011thensecond=3;elsifkeycode1=00100thensecond=4;elsifkeycode1=00101thensecond=

26、5;elsifkeycode1=00110thensecond=6;elsifkeycode1=00111thensecond=7;elsifkeycode1=01000thensecond=8;elsifkeycode1=01001thensecond=9;elsifkeycode1=00000thensecond=0;endif;n=n+1;elsifn=011andkeycode1=01101thenifysfh=0thenresult=first+second;elsifysfh=1thenresult=first-second;elsifysfh=2thenresult=first*

27、second;endif;n=n+1;elsifn=100thenn=000;endif;endif;endprocess;process(n)beginifn=001thenkeyvaluein=conv_std_logic_vector(first,8);elsifn=011thenkeyvaluein=conv_std_logic_vector(second,8);elsifn=100thenkeyvaluein=conv_std_logic_vector(result,8);ten:=0;one:=10;elsifnum0thenten:=0;one:=num;elsifnum9the

28、nten:=1;one:=num-10;elsifnum19thenten:=2;one:=num-20;elsifnum29thenten:=3;one:=num-30;elsifnum39thenten:=4;one:=num-40;elsifnum49thenten:=5;one:=num-50;elsifnum59thenten:=6;one:=num-60;elsifnum69thenten:=7;one:=num-70;elsifnum79thenten:=8;one:=num-80;elsifnum89thenten:=9;one:=num-90;endif;t=conv_std

29、_logic_vector(ten,4);oshow1show1show1show1show1show1show1show1show1show1show1show2show2show2show2show2show2show2show2show2show2show2=0000000;endcase;endif;endprocess;endshumaguanxianshi;動向顯示：鍵盤：libraryIEEE;libraryIEEE;useuseIEEE.STD_LOGIC_1164.ALL;IEEE.STD_LOGIC_1164.all;useIEEE.STD_LOGIC_ARITH.ALL;

30、useuseIEEE.STD_LOGIC_UNSIGNED.ALL;IEEE.STD_LOGIC_UNSIGNED.entitykeyboardisALL;Port(clr:instd_logic;useclk:inSTD_LOGIC;ieee.numeric_std.all;keyin:inSTD_LOGIC_VECTOR(3downto0);entityshaomiaoxianshikeydrv1:outstd_logic_vector(3downto0);iskeyvalue:outSTD_LOGIC_VECTOR(4downto0);port(clk,clr:instd_logic;s

31、tart:outstd_logic);show1:inendkeyboard;std_logic_vector(6downtoarchitectureRTLofkeyboardis0);componentkeyscanshow2:inPort(clkin,clr:inSTD_LOGIC;std_logic_vector(6downtokeydrv:outSTD_LOGIC_VECTOR(3downto0);0);endcomponent;showout:outcomponentkeydecoderstd_logic_vector(6downtoPort(clkin,clk,clr:instd_

32、logic;0);keyin:inSTD_LOGIC_VECTOR(3downto0);en:outkeycode:outSTD_LOGIC_VECTOR(4downtostd_logic_vector(7downto0);0);endcomponent;endshaomiaoxianshi;componentfangdouarchitectureport(keycode:instd_logic_vector(4downto0);shaomiaoxianshiofkeycode1:outstd_logic_vector(4downto0);shaomiaoxianshiisstart:outstd_logic;signalclk_f,clr:instd_logic);count:std_logic_vector(1endcomponent;downto0);componentfredivnbegingeneric(n:integer:=3);process(clk)Port(clkin:inSTD_LOGIC;beginclkout:outSTD_LOGIC);ifclr=1thencount=00;elseifclkeventandclk=1thenifcount=01thencount=00;elsec