先進(jìn)制造技術(shù)半導(dǎo)體制造裝備先進(jìn)制造技術(shù)半導(dǎo)體制造裝備1半導(dǎo)體制造裝備概述課件2半導(dǎo)體制造裝備概述課件3半導(dǎo)體制造裝備概述課件4微電子封裝一般可分為4級(jí),如圖所示,即:0級(jí)封裝———芯片上器件本體的互連1級(jí)封裝———芯片(1個(gè)或多個(gè))上的輸入/輸出與基板互連2級(jí)封裝———將封裝好的元器件或多芯片組件用多層互連布線板(ＰＷＢ)組裝成電子部件,插件或小整機(jī)3級(jí)封裝———用插件或小整機(jī)組裝成機(jī)柜整機(jī)系統(tǒng)微電子封裝一般可分為4級(jí),如圖所示,即:5半導(dǎo)體制造裝備概述課件6半導(dǎo)體制造裝備概述芯片制造（前道）單晶硅拉制、切片、表面處理、光刻、減薄、劃片芯片封裝（后道）測(cè)試、滴膠、Diebonding、Wirebonding、壓模半導(dǎo)體制造裝備概述芯片制造（前道）7半導(dǎo)體封裝的基本形式按其外部封裝型式分：雙列直插式封裝(ＤＩＰ)表面安裝技術(shù)(ＳＭＴ)

無引線陶瓷片式載體(ＬＣＣＣ)塑料有引線片式載體(ＰＬＣＣ)四邊引線扁平封裝(ＱＦＰ)四邊引線塑料扁平封裝(ＰＱＦＰ)平面陣列型(ＰＧＡ）球柵陣列封裝(ＢＧＡ)半導(dǎo)體封裝的基本形式8半導(dǎo)體制造裝備概述課件9半導(dǎo)體制造裝備概述課件10Chiptosubstrateinterconnecttechnologies按芯片的內(nèi)部連接方式來分Chiptosubstrateinterconnect11外引線鍵合外引線鍵合過程示意圖將帶引線的芯片從載帶上切下的示意圖外引線鍵合外引線鍵合過程示意圖將帶引線的芯片從載帶上切下的示12ＴＡＢ技術(shù)中的載帶ＴＡＢ技術(shù)中的載帶13概括而言,電子封裝技術(shù)已經(jīng)歷了四代,現(xiàn)正在進(jìn)入第五代。第一代：60年代前采用的是接線板焊接的方式,框架為電路板,主要插裝元件是電子管。第二代：60年代采用穿孔式印刷電路板(ＰＣＢ)封裝,主要元件是晶體管和柱型元件。第三代：70年代用自動(dòng)插裝方式將ＤＩＰ為代表的集成電路封裝在ＰＣＢ板上,這是穿孔式封裝技術(shù)的全盛時(shí)期。第四代：從80年代開始,采用ＳＭＴ將表面安裝元件(ＳＭＣ)和表面安裝器件(ＳＭＤ)安裝在ＰＣＢ表面上。這一封裝技術(shù)的革命改變了元器件和電子產(chǎn)品的面貌。第五代：這是90年代顯露頭角的微封裝技術(shù),是上一代封裝技術(shù)的發(fā)展和延伸,是將多層ＰＣＢ技術(shù)、高密度互連技術(shù)、ＳＭＴ、微型元器件封裝技術(shù)綜合并發(fā)展,其代表性技術(shù)就是金屬陶瓷封裝(ＭＣＰ),典型產(chǎn)品是ＭＣM。最近由于系統(tǒng)級(jí)芯片(ＳＯＣ)和全片規(guī)模集成(ＷＳＩ)技術(shù)的發(fā)展,微電子封裝技術(shù)正孕育著重大的突破概括而言,電子封裝技術(shù)已經(jīng)歷了四代,現(xiàn)正在進(jìn)入第五代。14半導(dǎo)體后封裝的發(fā)展趨勢(shì)向表面安裝技術(shù)(ＳＭＴ)發(fā)展1988年ＳＭＴ技術(shù)約占封裝市場(chǎng)份額的17.5%,1993年占44%,1998年占75%。傳統(tǒng)的雙列直插封裝所占份額越來越小,取而代之的是表面安裝類型的封裝,如有引線塑料片式載體,無引線陶瓷片式載體,四邊引線塑料扁平封裝,塑料球柵陣列封裝(ＰＢＧＡ)和陶瓷球柵陣列封裝(ＣＢＧＡ)等,尤其是ＰＱＦＰ和ＢＧＡ兩種類型最具典型.半導(dǎo)體后封裝的發(fā)展趨勢(shì)15向高密度發(fā)展目前,陶瓷外殼(ＣＣＧＡ)已達(dá)1089只管腳、ＣＢＧＡ達(dá)625只管腳、間距達(dá)0.5ｍｍ、ＰＱＦＰ達(dá)376只管腳、ＴＢＧＡ達(dá)1000只管腳。根據(jù)美國ＳＩＡ發(fā)展規(guī)劃,到2007年,最大芯片尺寸將增大到1000ｍｍ*2,同時(shí)每枚芯片上的輸入/輸出數(shù)最多將達(dá)到5000個(gè),焊點(diǎn)尺寸將縮小到0.127ｍｍ以下向高密度發(fā)展16從單芯片封裝向多芯片封裝發(fā)展ＭＣＭ起步于90年代初,由于ＭＣＭ的高密度、高性能和高可靠性而倍受青睞。受到世界各國的極大關(guān)注,紛紛投入巨額資金,如美國政府3年投入5億美元,ＩＢＭ在10年投入10億美元來發(fā)展ＭＣＭ,據(jù)預(yù)測(cè),1999年全球ＭＣＭ產(chǎn)品銷售額將達(dá)200億美元。目前最高水平的ＭＣＭ—Ｃ是ＩＢＭ的產(chǎn)品,200ｍｍ*2、78層、300多萬個(gè)通孔,1400ｍ互連線,1800只管腳,200Ｗ功耗從單芯片封裝向多芯片封裝發(fā)展17由陶瓷封裝向塑料封裝發(fā)展在陶瓷封裝向高密度,多引線和低功耗展的同時(shí),越來越多的領(lǐng)域正在由塑料封裝所取代。而且,新的塑料封裝形式層出不窮,目前以ＰＱＦＰ和ＰＢＧＡ為主,全部用于表面安裝,這些塑料封裝占領(lǐng)著90%以上的市場(chǎng)由陶瓷封裝向塑料封裝發(fā)展18高密度封裝中的關(guān)鍵技術(shù)從技術(shù)發(fā)展觀點(diǎn)來看,作為高密度封裝的關(guān)鍵技術(shù)主要有:ＴＣＰ,ＢＧＡ,ＦＣＴ,ＣＳＰ,ＭＣＭ和三維封裝載帶封裝

它可以提供超窄的引線間距和很薄的封裝外形,且在ＰＣＢ板上占據(jù)很小的面積,可用于高Ｉ/Ｏ數(shù)的ＡＳＩＣ和微處理器,東芝公司1996年問世的筆記本電腦中就使用了ＴＣＰ承載ＣＰＵ,其引線間距0.25ｍｍ,焊接精度為±30μｍ,據(jù)報(bào)道,最小間距可達(dá)0.15ｍｍ高密度封裝中的關(guān)鍵技術(shù)載帶封裝19球柵陣列封裝(BGA)ＢＧＡ技術(shù)的最大特點(diǎn)是器件與ＰＣＢ板之間的互連由引線改為小球,制作小球的材料通常采用合金焊料或有機(jī)導(dǎo)電樹脂。采用ＢＧＡ技術(shù)容易獲得Ｉ/Ｏ數(shù)超過600個(gè)的封裝體。由于ＢＧＡ完全采用與ＱＦＰ相同的ＳＭＴ回流焊工藝,避免了ＱＦＰ中的超窄間距,可以提供較大的焊盤區(qū),因此使焊接工藝更加簡(jiǎn)單,強(qiáng)度大大提高,可靠性明顯改善球柵陣列封裝(BGA)20ＢＧＡ的尺寸通常大于ＣＳＰ(芯片規(guī)模封裝),在21～40ｍｍ之間?？煞譃樗芰希拢牵?ＰＢＧＡ)、陶瓷ＢＧＡ(ＣＢＧＡ)或載帶ＢＧＡ(ＴＢＧＡ)。在ＰＢＧＡ中,通常用引線鍵合采用焊球或引線鍵合將芯片貼在陶瓷基板上;在ＴＢＧＡ中,用標(biāo)準(zhǔn)ＴＡＢ內(nèi)引線鍵合工藝或焊球?qū)⑿酒N在其帶狀框架上ＢＧＡ的尺寸通常大于ＣＳＰ(芯片規(guī)模封裝),在21～21半導(dǎo)體制造裝備概述課件22半導(dǎo)體制造裝備概述課件23芯片規(guī)模封裝與芯片尺寸封裝(ＣＳＰ)芯片規(guī)模封裝與芯片尺寸封裝統(tǒng)稱為ＣＳＰ,它被認(rèn)為是本世紀(jì)先進(jìn)封裝的主流技術(shù)。在芯片規(guī)模封裝中,封裝體的尺寸是芯片尺寸的1.2倍以下;芯片尺寸封裝中封裝體的尺寸與芯片尺寸基本相當(dāng)。這是在電路板面積不變的前提下,希望更換大芯片的集成電路時(shí)提出的。在這種情況下,將框架引線伸展到芯片上方形成芯片引線(ＬＯＣ),封裝尺寸不變,芯片面積增大,封裝體面積與芯片面積的比值變小芯片規(guī)模封裝與芯片尺寸封裝(ＣＳＰ)24半導(dǎo)體制造裝備概述課件25多芯片組件(ＭＣＭ)將多只合格的裸芯片(ＫＧＤ)直接封裝在多層互連基板上,并與其它元器件一起構(gòu)成具有部件或系統(tǒng)功能的多芯片組件(ＭＣＭ),已成為蜚聲全球的90年代代表性技術(shù)。多芯片組件(ＭＣＭ)26半導(dǎo)體制造裝備概述課件27MCM封裝MCM封裝28COB----ChipOnBoardCOB----ChipOnBoard29半導(dǎo)體制造裝備概述課件30ChiponBoard----COBChiponBoard----COB31DieBondingDieBonding32半導(dǎo)體制造裝備概述課件33半導(dǎo)體制造裝備概述課件34半導(dǎo)體制造裝備概述課件35HistoryandapplicationsofwirebondingWirebondingistheearliesttechniqueofdeviceassembly,whosefirstresultwaspublishedbyBellLaboratoriesin1957.Sinethen,thetechniquehasbeenextremelydevelopedHistoryandapplicationsofwi36AdvantageFullyautomaticmachineshavebeendevelopedforvolumeproduction.Bondingparameterscanbepreciselycontrolled;mechanicalpropertiesofwirescanbehighlyreproduced.Bondingspeedcanreach100-125mspereachwireinterconnection(twoweldsandawireloop).Mostreliabilityproblemscanbeeliminatedwithproperlycontrolledandmuchimprovedtools(capillariesandwedges)andprocesses.Specificbondingtoolsandwirescanbeselectedbypackagingengineerstomeettherequirements.Infrastructureofthetechniquehasbeencomprisedbylargewirebondingknowledge,manufacturingpeople,equipmentvendersandmaterials.AdvantageFullyautomaticmachi37Themostpopularapplicationsthatusewirebondingare:Singleandmultitieredcofiredceramicandplasticballgridarrays(BGAs),singlechipandmultichipCeramicandplasticquadflatpackages(CerQuadsandPQFPs)Chipscalepackages(CSPs)Chiponboard(COB)Themostpopularapplications38BallbondWedgebondWirebonding的基本形式BallbondWedgebondWirebonding39Firstandsecondbondcomparison.(A)Ballbondingfirstbond.(B)Ballbondingsecondbond:stitchbondandtailbond.(C)Wedgebondingfirstbond.(D)Wedgebondingsecondbond.Firstandsecondbondcomparis40半導(dǎo)體制造裝備概述課件41Wedgebondthebondingprocesscanbedefinedtothreemajorprocesses:

thermocompressionbonding(T/C)ultrasonicbonding(U/S)thermosonicbonding(T/S)asshowninTable1-1Wedgebond42半導(dǎo)體制造裝備概述課件43半導(dǎo)體制造裝備概述課件44BallBondingBallBonding45Thecapillariesaretypically1.585mmindiameterand11.1mmlong.Theyhavealargeentryholeatthetopandthentheholetapersdowntoasmallholediametertypicallybetween38-50mm,Thecapillariesaretypically4640-μmpadpitchballandwedgefirstbondcomparison.40-μmpadpitchballand47Schematicofdifferentlooping.(A)Ballbondinglooping.(B)Traditionalwedgeradialbondinglooping.(C)WedgebondingConstantGaplooping.Schematicofdifferentlooping4840mmpitchfirstbond.40mmpitchfirstbond.4940mmlooping.Shortwiresaretoground.Longwiresaretotheleads.40mmlooping.Shortwiresare50Wedgestitchbonding.Wedgestitchbonding.51半導(dǎo)體制造裝備概述課件52半導(dǎo)體制造裝備概述課件53半導(dǎo)體制造裝備概述課件54半導(dǎo)體制造裝備概述課件55LimitationofwirebondingFortheapplicationofwirebondingmethod,terminalsofchipshavetobearrangedattheperipheryofthechips,otherwiseshortcircuitiseasilycaused.Therefore,wirebondingtechniqueisdifficultforhighI/O(>500)interconnections.Limitationofwirebonding56BondingparametersBondingparametersareextremelyimportantbecausetheycontrolthebondingyieldandreliabilitydirectly.Thekeyvariablesforwirebondinginclude:·Bondingforceandpressureuniformity·Bondingtemperature·Bondingtime·UltrasonicfrequencyandpowerBondingparameters57BonddesignBallbonding·Ballsizeisapproximately2to3timesthewirediameter,1.5timesforsmallballapplicationswithfinepitches,and3to4timesforlargebondpadapplication.·Bondsizeshouldnotexceed3/4ofthepadsize,about2.5to5timesthewirediameter,dependingonthegeometryandmovingdirectionofcapillaryduringbonding.·Loopheightsof150umarenowcommon,butverydependingonthewirediameterandapplications.·Looplengthshouldbelessthan100timesthewirediameter.However,insomecases,highI/Osforinstance,wirelengthshavetoincreasetomorethan5mm.Thewirebondermustsuspendthelengthofwirebetweenthedieandleadframewithoutverticalsaggingorhorizontalswaying.Bonddesign58Wedgebonding·Ahigh-strengthwedgebondispossibleeventhebondisonly2-3mmwiderthanwirediameter.·Padlengthmustsupportthelongdimensionofthewedgebondaswellasthetail.·Thepad'slongaxisshouldbeorientedalongtheintendedwirepath.·Bondpitchmustbedesignedtomaintainconsistentdistancebetweenwires.Wedgebonding59CleaningToensurebondabilityandreliabilityofwirebond,oneofthecriticalconditionsisthatthebondingsurfacemustbefreeofanycontaminants.Thereforecleaningisanimportantworkbeforebonding.Themethodusuallyadaptedismolecularcleaningmethod,plasmaorUV-ozonecleaningmethod.Cleaning60BondevaluationDestructivebondpulltest(Method2011)Internalvisual(Method2010;TestconditionAandB)Delaymeasurements(Method3003)Nondestructivebondpulltest(Method2023)BallbondsheartestConstantacceleration(Method2001;TestconditionE)Randomvibration(Method2026)Mechanicalshock(Method2002)Stabilizationbake(Method1008)Moistureresistance(Method1004)Bondevaluation61Destructivebondpulltest(Method2011)Destructivebondpulltest(Me62Ifboththebondsareatthesamelevelandthehookisappliedatthecenter,theforcescanberepresentedWhenthebothanglesare30o,thepullforceisequaltothebreakload.Thefailureduringpulltestmayoccuratoneofthefivepositionsinthewirebondstructure:A.LiftofffirstbondB.WirebreakattransitionfirstbondC.WirebreakmidspanD.WirebreakattransitionsecondbondE.LiftoffsecondbondWhenproperlypulled,thebondshouldfailatBorD.IffailuresoccuratA,C,orE,thenthebondingparameters,metallization,bondingmachine,bondingtool,hook,hastobereviewed.Ifboththebondsareatthesa63Flip-ChipTechnologyFlip-ChipTechnology64Advantages:·Smallersize:SmallerICfootprint(onlyabout5%ofthatofpackagedICe.g.quadflatpack),reducedheightandweight.·Increasedfunctionality:TheuseofflipchipsallowanincreaseinthenumberofI/O.I/Oisnotlimitedtotheperimeterofthechipasinwirebonding.Anareaarraypadlayoutenablesmoresignal,powerandgroundconnectionsinlessspace.Aflipchipcaneasilyhandlemorethan400pads.·Improvedperformance:Shortinterconnectdeliverslowinductance,resistanceandcapacitance,smallelectricaldelays,goodhighfrequencycharacteristics,thermalpathfromthebacksideofthedie.·Improvedreliability:Epoxyunderfillinlargechipsensureshighreliability.Flip-chipscanreducethenumberconnectionsperpinfromthreetoone.·Improvedthermalcapabilities:Becauseflipchipsarenotencapsulated,thebacksideofthechipcanbeusedforefficientcooling.·Lowcost:Batchbumpingprocess,costofbumpingdecreases,costreductionsintheunderfill-processAdvantages:65Disadvantages:·Difficulttestingofbaredies.·Limitedavailabilityofbumpedchips.·ChallengeforPCBtechnologyaspitchesbecomeveryfineandbumpcountsarehigh.·ForinspectionofhiddenjointsanX-rayequipmentisneeded.·WeakprocesscompatibilitywithSMT.·Handlingofbarechipsisdifficult.·Highassemblyaccuracyneeded.·Withpresentdaymaterialsunderfillingprocesswithaconsiderablecuringtimeisneeded.·Lowreliabilityforsomesubstrates.·Repairingisdifficultorimpossible.Disadvantages:66底部填充工藝(UnderfillingProcess）溫度膨脹系數(shù)小于3ppm/℃的硅器件直接同有機(jī)物印制線路板(溫度膨脹系數(shù)在18～50ppm/℃)壓接在一起,會(huì)產(chǎn)生嚴(yán)重的熱機(jī)應(yīng)力和疲勞,俗稱“熱機(jī)失配底部填充料鎖住倒裝片和印制板示意圖底部填充工藝(UnderfillingProcess）底67半導(dǎo)體制造裝備概述課件68Flipchipjoiningusingadhesives(isotropic,anisotropic,nonconductive)Flipchipjoiningusingadhesi69Flipchipjoiningbythermocompression.FlipchipthermosonicjoiningFlipchipjoiningbythermocom70FlipchipbondingusingthermocompressionFlipchipbondingusingthermo71Flipchipprocessbysolderjoining·diepreparing(testing,bumping,dicing)·substratepreparing(fluxapplicationorsolderpasteprinting)·pick,alignmentandplace·reflowsoldering·cleaningoffluxresidues(optional)·underfilldispensing·underfillcuring.Flipchipprocessbysolderjo72半導(dǎo)體制造裝備概述課件73半導(dǎo)體制造裝備概述課件74半導(dǎo)體制造裝備概述課件75半導(dǎo)體制造裝備概述課件76FlipchipjoiningusingadhesivesFlipchipjoiningusingadhesi77半導(dǎo)體制造裝備概述課件78IntroductiontoCSPTechnologyDescriptionofvarioustypesofCSPsIntroductiontoCSPTechnology79半導(dǎo)體制造裝備概述課件80BallGridArray(BGA)TechnologyBallGridArray(BGA)Technolo81ItisanICpackageforactivedevicesintendedforsurfacemountapplicationsItisanareaarraypackage,i.e.utilizingwholeorpartofthedevicefootprintforinterconnectionsTheinterconnectionsaremadeofballs(spheres)ofmostoftenasolderalloyorsometimesothermetalsMorespecifically,theBGApackageusuallyfulfilsthefollowingadditionalrequirements:Thelengthofthepackagebody(mostoftensquare)rangesfrom7to50mmLeadcountsover1000possible,but50to500rangemostcommontodayThepitch,i.ecenter-to-centerdistance,oftheballsisgenerallybetween1.0and1.5mmItisanICpackageforactive82Figure2.A160-lead0.3mm(11.8mil)pitchQFPplacedonagridof1.5mmpitchspheres(bottomsideofaPBGAS225).Figure2.A160-lead0.3mm(183半導(dǎo)體制造裝備概述課件84半導(dǎo)體制造裝備概述課件85Figure5.Across-sectionofaTape(orTAB)BGA-TBGA.Figure5.Across-sectionofa86Across-sectionofaSuperBGA-SBGA.Across-sectionofaSuperBGA87半導(dǎo)體制造裝備概述課件88半導(dǎo)體制造裝備概述課件89半導(dǎo)體制造裝備概述課件90半導(dǎo)體制造裝備概述課件91半導(dǎo)體制造裝備概述課件92先進(jìn)制造技術(shù)半導(dǎo)體制造裝備先進(jìn)制造技術(shù)半導(dǎo)體制造裝備93半導(dǎo)體制造裝備概述課件94半導(dǎo)體制造裝備概述課件95半導(dǎo)體制造裝備概述課件96微電子封裝一般可分為4級(jí),如圖所示,即:0級(jí)封裝———芯片上器件本體的互連1級(jí)封裝———芯片(1個(gè)或多個(gè))上的輸入/輸出與基板互連2級(jí)封裝———將封裝好的元器件或多芯片組件用多層互連布線板(ＰＷＢ)組裝成電子部件,插件或小整機(jī)3級(jí)封裝———用插件或小整機(jī)組裝成機(jī)柜整機(jī)系統(tǒng)微電子封裝一般可分為4級(jí),如圖所示,即:97半導(dǎo)體制造裝備概述課件98半導(dǎo)體制造裝備概述芯片制造（前道）單晶硅拉制、切片、表面處理、光刻、減薄、劃片芯片封裝（后道）測(cè)試、滴膠、Diebonding、Wirebonding、壓模半導(dǎo)體制造裝備概述芯片制造（前道）99半導(dǎo)體封裝的基本形式按其外部封裝型式分：雙列直插式封裝(ＤＩＰ)表面安裝技術(shù)(ＳＭＴ)

無引線陶瓷片式載體(ＬＣＣＣ)塑料有引線片式載體(ＰＬＣＣ)四邊引線扁平封裝(ＱＦＰ)四邊引線塑料扁平封裝(ＰＱＦＰ)平面陣列型(ＰＧＡ）球柵陣列封裝(ＢＧＡ)半導(dǎo)體封裝的基本形式100半導(dǎo)體制造裝備概述課件101半導(dǎo)體制造裝備概述課件102Chiptosubstrateinterconnecttechnologies按芯片的內(nèi)部連接方式來分Chiptosubstrateinterconnect103外引線鍵合外引線鍵合過程示意圖將帶引線的芯片從載帶上切下的示意圖外引線鍵合外引線鍵合過程示意圖將帶引線的芯片從載帶上切下的示104ＴＡＢ技術(shù)中的載帶ＴＡＢ技術(shù)中的載帶105概括而言,電子封裝技術(shù)已經(jīng)歷了四代,現(xiàn)正在進(jìn)入第五代。第一代：60年代前采用的是接線板焊接的方式,框架為電路板,主要插裝元件是電子管。第二代：60年代采用穿孔式印刷電路板(ＰＣＢ)封裝,主要元件是晶體管和柱型元件。第三代：70年代用自動(dòng)插裝方式將ＤＩＰ為代表的集成電路封裝在ＰＣＢ板上,這是穿孔式封裝技術(shù)的全盛時(shí)期。第四代：從80年代開始,采用ＳＭＴ將表面安裝元件(ＳＭＣ)和表面安裝器件(ＳＭＤ)安裝在ＰＣＢ表面上。這一封裝技術(shù)的革命改變了元器件和電子產(chǎn)品的面貌。第五代：這是90年代顯露頭角的微封裝技術(shù),是上一代封裝技術(shù)的發(fā)展和延伸,是將多層ＰＣＢ技術(shù)、高密度互連技術(shù)、ＳＭＴ、微型元器件封裝技術(shù)綜合并發(fā)展,其代表性技術(shù)就是金屬陶瓷封裝(ＭＣＰ),典型產(chǎn)品是ＭＣM。最近由于系統(tǒng)級(jí)芯片(ＳＯＣ)和全片規(guī)模集成(ＷＳＩ)技術(shù)的發(fā)展,微電子封裝技術(shù)正孕育著重大的突破概括而言,電子封裝技術(shù)已經(jīng)歷了四代,現(xiàn)正在進(jìn)入第五代。106半導(dǎo)體后封裝的發(fā)展趨勢(shì)向表面安裝技術(shù)(ＳＭＴ)發(fā)展1988年ＳＭＴ技術(shù)約占封裝市場(chǎng)份額的17.5%,1993年占44%,1998年占75%。傳統(tǒng)的雙列直插封裝所占份額越來越小,取而代之的是表面安裝類型的封裝,如有引線塑料片式載體,無引線陶瓷片式載體,四邊引線塑料扁平封裝,塑料球柵陣列封裝(ＰＢＧＡ)和陶瓷球柵陣列封裝(ＣＢＧＡ)等,尤其是ＰＱＦＰ和ＢＧＡ兩種類型最具典型.半導(dǎo)體后封裝的發(fā)展趨勢(shì)107向高密度發(fā)展目前,陶瓷外殼(ＣＣＧＡ)已達(dá)1089只管腳、ＣＢＧＡ達(dá)625只管腳、間距達(dá)0.5ｍｍ、ＰＱＦＰ達(dá)376只管腳、ＴＢＧＡ達(dá)1000只管腳。根據(jù)美國ＳＩＡ發(fā)展規(guī)劃,到2007年,最大芯片尺寸將增大到1000ｍｍ*2,同時(shí)每枚芯片上的輸入/輸出數(shù)最多將達(dá)到5000個(gè),焊點(diǎn)尺寸將縮小到0.127ｍｍ以下向高密度發(fā)展108從單芯片封裝向多芯片封裝發(fā)展ＭＣＭ起步于90年代初,由于ＭＣＭ的高密度、高性能和高可靠性而倍受青睞。受到世界各國的極大關(guān)注,紛紛投入巨額資金,如美國政府3年投入5億美元,ＩＢＭ在10年投入10億美元來發(fā)展ＭＣＭ,據(jù)預(yù)測(cè),1999年全球ＭＣＭ產(chǎn)品銷售額將達(dá)200億美元。目前最高水平的ＭＣＭ—Ｃ是ＩＢＭ的產(chǎn)品,200ｍｍ*2、78層、300多萬個(gè)通孔,1400ｍ互連線,1800只管腳,200Ｗ功耗從單芯片封裝向多芯片封裝發(fā)展109由陶瓷封裝向塑料封裝發(fā)展在陶瓷封裝向高密度,多引線和低功耗展的同時(shí),越來越多的領(lǐng)域正在由塑料封裝所取代。而且,新的塑料封裝形式層出不窮,目前以ＰＱＦＰ和ＰＢＧＡ為主,全部用于表面安裝,這些塑料封裝占領(lǐng)著90%以上的市場(chǎng)由陶瓷封裝向塑料封裝發(fā)展110高密度封裝中的關(guān)鍵技術(shù)從技術(shù)發(fā)展觀點(diǎn)來看,作為高密度封裝的關(guān)鍵技術(shù)主要有:ＴＣＰ,ＢＧＡ,ＦＣＴ,ＣＳＰ,ＭＣＭ和三維封裝載帶封裝

它可以提供超窄的引線間距和很薄的封裝外形,且在ＰＣＢ板上占據(jù)很小的面積,可用于高Ｉ/Ｏ數(shù)的ＡＳＩＣ和微處理器,東芝公司1996年問世的筆記本電腦中就使用了ＴＣＰ承載ＣＰＵ,其引線間距0.25ｍｍ,焊接精度為±30μｍ,據(jù)報(bào)道,最小間距可達(dá)0.15ｍｍ高密度封裝中的關(guān)鍵技術(shù)載帶封裝111球柵陣列封裝(BGA)ＢＧＡ技術(shù)的最大特點(diǎn)是器件與ＰＣＢ板之間的互連由引線改為小球,制作小球的材料通常采用合金焊料或有機(jī)導(dǎo)電樹脂。采用ＢＧＡ技術(shù)容易獲得Ｉ/Ｏ數(shù)超過600個(gè)的封裝體。由于ＢＧＡ完全采用與ＱＦＰ相同的ＳＭＴ回流焊工藝,避免了ＱＦＰ中的超窄間距,可以提供較大的焊盤區(qū),因此使焊接工藝更加簡(jiǎn)單,強(qiáng)度大大提高,可靠性明顯改善球柵陣列封裝(BGA)112ＢＧＡ的尺寸通常大于ＣＳＰ(芯片規(guī)模封裝),在21～40ｍｍ之間?？煞譃樗芰希拢牵?ＰＢＧＡ)、陶瓷ＢＧＡ(ＣＢＧＡ)或載帶ＢＧＡ(ＴＢＧＡ)。在ＰＢＧＡ中,通常用引線鍵合采用焊球或引線鍵合將芯片貼在陶瓷基板上;在ＴＢＧＡ中,用標(biāo)準(zhǔn)ＴＡＢ內(nèi)引線鍵合工藝或焊球?qū)⑿酒N在其帶狀框架上ＢＧＡ的尺寸通常大于ＣＳＰ(芯片規(guī)模封裝),在21～113半導(dǎo)體制造裝備概述課件114半導(dǎo)體制造裝備概述課件115芯片規(guī)模封裝與芯片尺寸封裝(ＣＳＰ)芯片規(guī)模封裝與芯片尺寸封裝統(tǒng)稱為ＣＳＰ,它被認(rèn)為是本世紀(jì)先進(jìn)封裝的主流技術(shù)。在芯片規(guī)模封裝中,封裝體的尺寸是芯片尺寸的1.2倍以下;芯片尺寸封裝中封裝體的尺寸與芯片尺寸基本相當(dāng)。這是在電路板面積不變的前提下,希望更換大芯片的集成電路時(shí)提出的。在這種情況下,將框架引線伸展到芯片上方形成芯片引線(ＬＯＣ),封裝尺寸不變,芯片面積增大,封裝體面積與芯片面積的比值變小芯片規(guī)模封裝與芯片尺寸封裝(ＣＳＰ)116半導(dǎo)體制造裝備概述課件117多芯片組件(ＭＣＭ)將多只合格的裸芯片(ＫＧＤ)直接封裝在多層互連基板上,并與其它元器件一起構(gòu)成具有部件或系統(tǒng)功能的多芯片組件(ＭＣＭ),已成為蜚聲全球的90年代代表性技術(shù)。多芯片組件(ＭＣＭ)118半導(dǎo)體制造裝備概述課件119MCM封裝MCM封裝120COB----ChipOnBoardCOB----ChipOnBoard121半導(dǎo)體制造裝備概述課件122ChiponBoard----COBChiponBoard----COB123DieBondingDieBonding124半導(dǎo)體制造裝備概述課件125半導(dǎo)體制造裝備概述課件126半導(dǎo)體制造裝備概述課件127HistoryandapplicationsofwirebondingWirebondingistheearliesttechniqueofdeviceassembly,whosefirstresultwaspublishedbyBellLaboratoriesin1957.Sinethen,thetechniquehasbeenextremelydevelopedHistoryandapplicationsofwi128AdvantageFullyautomaticmachineshavebeendevelopedforvolumeproduction.Bondingparameterscanbepreciselycontrolled;mechanicalpropertiesofwirescanbehighlyreproduced.Bondingspeedcanreach100-125mspereachwireinterconnection(twoweldsandawireloop).Mostreliabilityproblemscanbeeliminatedwithproperlycontrolledandmuchimprovedtools(capillariesandwedges)andprocesses.Specificbondingtoolsandwirescanbeselectedbypackagingengineerstomeettherequirements.Infrastructureofthetechniquehasbeencomprisedbylargewirebondingknowledge,manufacturingpeople,equipmentvendersandmaterials.AdvantageFullyautomaticmachi129Themostpopularapplicationsthatusewirebondingare:Singleandmultitieredcofiredceramicandplasticballgridarrays(BGAs),singlechipandmultichipCeramicandplasticquadflatpackages(CerQuadsandPQFPs)Chipscalepackages(CSPs)Chiponboard(COB)Themostpopularapplications130BallbondWedgebondWirebonding的基本形式BallbondWedgebondWirebonding131Firstandsecondbondcomparison.(A)Ballbondingfirstbond.(B)Ballbondingsecondbond:stitchbondandtailbond.(C)Wedgebondingfirstbond.(D)Wedgebondingsecondbond.Firstandsecondbondcomparis132半導(dǎo)體制造裝備概述課件133Wedgebondthebondingprocesscanbedefinedtothreemajorprocesses:

thermocompressionbonding(T/C)ultrasonicbonding(U/S)thermosonicbonding(T/S)asshowninTable1-1Wedgebond134半導(dǎo)體制造裝備概述課件135半導(dǎo)體制造裝備概述課件136BallBondingBallBonding137Thecapillariesaretypically1.585mmindiameterand11.1mmlong.Theyhavealargeentryholeatthetopandthentheholetapersdowntoasmallholediametertypicallybetween38-50mm,Thecapillariesaretypically13840-μmpadpitchballandwedgefirstbondcomparison.40-μmpadpitchballand139Schematicofdifferentlooping.(A)Ballbondinglooping.(B)Traditionalwedgeradialbondinglooping.(C)WedgebondingConstantGaplooping.Schematicofdifferentlooping14040mmpitchfirstbond.40mmpitchfirstbond.14140mmlooping.Shortwiresaretoground.Longwiresaretotheleads.40mmlooping.Shortwiresare142Wedgestitchbonding.Wedgestitchbonding.143半導(dǎo)體制造裝備概述課件144半導(dǎo)體制造裝備概述課件145半導(dǎo)體制造裝備概述課件146半導(dǎo)體制造裝備概述課件147LimitationofwirebondingFortheapplicationofwirebondingmethod,terminalsofchipshavetobearrangedattheperipheryofthechips,otherwiseshortcircuitiseasilycaused.Therefore,wirebondingtechniqueisdifficultforhighI/O(>500)interconnections.Limitationofwirebonding148BondingparametersBondingparametersareextremelyimportantbecausetheycontrolthebondingyieldandreliabilitydirectly.Thekeyvariablesforwirebondinginclude:·Bondingforceandpressureuniformity·Bondingtemperature·Bondingtime·UltrasonicfrequencyandpowerBondingparameters149BonddesignBallbonding·Ballsizeisapproximately2to3timesthewirediameter,1.5timesforsmallballapplicationswithfinepitches,and3to4timesforlargebondpadapplication.·Bondsizeshouldnotexceed3/4ofthepadsize,about2.5to5timesthewirediameter,dependingonthegeometryandmovingdirectionofcapillaryduringbonding.·Loopheightsof150umarenowcommon,butverydependingonthewirediameterandapplications.·Looplengthshouldbelessthan100timesthewirediameter.However,insomecases,highI/Osforinstance,wirelengthshavetoincreasetomorethan5mm.Thewirebondermustsuspendthelengthofwirebetweenthedieandleadframewithoutverticalsaggingorhorizontalswaying.Bonddesign150Wedgebonding·Ahigh-strengthwedgebondispossibleeventhebondisonly2-3mmwiderthanwirediameter.·Padlengthmustsupportthelongdimensionofthewedgebondaswellasthetail.·Thepad'slongaxisshouldbeorientedalongtheintendedwirepath.·Bondpitchmustbedesignedtomaintainconsistentdistancebetweenwires.Wedgebonding151CleaningToensurebondabilityandreliabilityofwirebond,oneofthecriticalconditionsisthatthebondingsurfacemustbefreeofanycontaminants.Thereforecleaningisanimportantworkbeforebonding.Themethodusuallyadaptedismolecularcleaningmethod,plasmaorUV-ozonecleaningmethod.Cleaning152BondevaluationDestructivebondpulltest(Method2011)Internalvisual(Method2010;TestconditionAandB)Delaymeasurements(Method3003)Nondestructivebondpulltest(Method2023)BallbondsheartestConstantacceleration(Method2001;TestconditionE)Randomvibration(Method2026)Mechanicalshock(Method2002)Stabilizationbake(Method1008)Moistureresistance(Method1004)Bondevaluation153Destructivebondpulltest(Method2011)Destructivebondpulltest(Me154Ifboththebondsareatthesamelevelandthehookisappliedatthecenter,theforcescanberepresentedWhenthebothanglesare30o,thepullforceisequaltothebreakload.Thefailureduringpulltestmayoccuratoneofthefivepositionsinthewirebondstructure:A.LiftofffirstbondB.WirebreakattransitionfirstbondC.WirebreakmidspanD.WirebreakattransitionsecondbondE.LiftoffsecondbondWhenproperlypulled,thebondshouldfailatBorD.IffailuresoccuratA,C,orE,thenthebondingparameters,metallization,bondingmachine,bondingtool,hook,hastobereviewed.Ifboththebondsareatthesa155Flip-ChipTechnologyFlip-ChipTechnology156Advantages:·Smallersize:SmallerICfootprint(onlyabout5%ofthatofpackagedICe.g.quadflatpack),reducedheightandweight.·Increasedfunctionality:TheuseofflipchipsallowanincreaseinthenumberofI/O.I/Oisnotlimitedtotheperimeterofthechipasinwirebonding.Anareaarraypadlayoutenablesmoresignal,powerandgroundconnectionsinlessspace.Aflipchipcaneasilyhandlemorethan400pads.·Improvedperformance:Shortinterconnectdeliverslowinductance,resistanceandcapacitance,smallelectricaldelays,goodhighfrequencycharacteristics,thermalpathfromthebacksideofthedie.·Improvedreliability:Epoxyunderfillinlargechipsensureshighreliability.Flip-chipscanreducethenumberconnectionsperpinfromthreetoone.·Improvedthermalcapabilities:Becauseflipchipsarenotencapsulated,thebacksideofthechipcanbeusedforefficientcooling.·Lowcost:Batchbumpingprocess,costofbumpingdecreases,costreductionsintheunderfill-processAdvantages:157Disadvantages:·Difficulttestingofbaredies.·Limitedavailabilityofbumpedchips.·ChallengeforPCBtechnologyaspitchesbecomeveryfineandbumpcountsarehigh.·Forins