第1章嵌入式系統(tǒng)與ARM處理器目錄處理器的種類1嵌入式系統(tǒng)2ARM處理器3ARM的產(chǎn)品系列4ARM的應(yīng)用領(lǐng)域51.1嵌入式系統(tǒng)概念嵌入式系統(tǒng) 以應(yīng)用為中心，以計(jì)算機(jī)技術(shù)為基礎(chǔ)，軟硬件可裁減，以適應(yīng)應(yīng)用系統(tǒng)對(duì)功能、可靠性、成本、體積和功耗等有嚴(yán)格要求的專用計(jì)算機(jī)系統(tǒng)。嵌入式系統(tǒng)組成硬件：微處理器、存儲(chǔ)器、I/O接口、輸入輸出設(shè)備。軟件：Embedded

RTOS、應(yīng)用軟件。1.2嵌入式系統(tǒng)的硬件組成最小系統(tǒng)電源模塊時(shí)鐘模塊復(fù)位電路微處理器MPUFlashSDRAMJTAG外設(shè)USBLCD鍵盤串口以太網(wǎng)CAN傳感器電機(jī)輔助存儲(chǔ)器USBLCD鍵盤串口以太網(wǎng)1.3嵌入式系統(tǒng)的軟件結(jié)構(gòu)應(yīng)用程序Application設(shè)備驅(qū)動(dòng)程序Driver硬件（單片機(jī)）應(yīng)用（Application）標(biāo)準(zhǔn)接口函數(shù)（API）實(shí)時(shí)操作系統(tǒng)（RTOS）硬件抽象層（HAL）BSP、驅(qū)動(dòng)硬件（微處理器）不帶OS軟件結(jié)構(gòu)

帶OS軟件結(jié)構(gòu)1.4嵌入式系統(tǒng)的特性硬件特性體積小、集成效率高。面向特定的應(yīng)用。功耗低、電磁兼容性好。軟件特性嵌入式軟件的開發(fā)與硬件緊密相關(guān)。軟件代碼要求高效率和高可靠性。軟件一般固化在Flash或Rom中。軟件系統(tǒng)具有高實(shí)時(shí)性。一般采用C語(yǔ)言開發(fā)。1.5嵌入式系統(tǒng)設(shè)計(jì)流程1.需求分析2.體系結(jié)構(gòu)設(shè)計(jì)3.硬件的設(shè)計(jì)、制作及測(cè)試3.軟件的設(shè)計(jì)、實(shí)現(xiàn)及測(cè)試4.系統(tǒng)集成5.系統(tǒng)性能測(cè)試及可靠性測(cè)試6.工業(yè)試運(yùn)行及生產(chǎn)文件準(zhǔn)備7.項(xiàng)目總結(jié)2.1嵌入式微處理器嵌入式系統(tǒng)上的處理器單元稱為嵌入式微處理器。嵌入式微處理器是嵌入式系統(tǒng)硬件的核心、運(yùn)行嵌入式系統(tǒng)的系統(tǒng)軟件和應(yīng)用軟件。嵌入式微處理器處理器內(nèi)核地址總線數(shù)據(jù)總線控制類總線片上I/O接口電路時(shí)鐘、復(fù)位電路等通信、控制等模塊2.2嵌入式微處理器的種類X86Core

－－Intel公司（工控機(jī)）ColdFire－－Motorola（工業(yè)控制）PowerPC

－－IBM&Motorola&apple（交換設(shè)備）MIPS－－只設(shè)計(jì)內(nèi)核的一家美國(guó)公司（高性能）ARM－－只設(shè)計(jì)內(nèi)核的一家英國(guó)公司（一般應(yīng)用）DSP－－TI（運(yùn)動(dòng)控制、算術(shù)運(yùn)算）2.3嵌入式微處理器的特點(diǎn)價(jià)格便宜特定的功能體積小能耗低使用方便3.1什么是ARMARM－－AdvancedRISCMachineARM是英國(guó)一家電子公司的名字ARM敢為天下先，首創(chuàng)了chipless的生產(chǎn)模式，即該公司既不生產(chǎn)芯片，也不設(shè)計(jì)芯片，而是設(shè)計(jì)出高效的IP內(nèi)核，授權(quán)給半導(dǎo)體公司使用。

ARM提供一系列內(nèi)核、體系擴(kuò)展、微處理器和系統(tǒng)芯片方案ARM是一種通用的32位RISC處理器ARM是一種功耗很低的高性能處理器3.2ARM公司成立于1990年11月前身為Acorn計(jì)算機(jī)公司設(shè)計(jì)ARM系列RISC處理器內(nèi)核授權(quán)ARM內(nèi)核給生產(chǎn)和銷售半導(dǎo)體的合作伙伴ARM公司不生產(chǎn)芯片提供基于ARM架構(gòu)的開發(fā)設(shè)計(jì)技術(shù)軟件工具,評(píng)估板,調(diào)試工具,應(yīng)用軟件,總線架構(gòu),外圍設(shè)備單元，等等3.3ARM合作伙伴3.4ARM處理器的特點(diǎn)體積小、低功耗、低成本、高性能；支持Thumb(16位)和ARM(32位)雙指令集；大量使用寄存器，指令執(zhí)行速度更快；大多數(shù)數(shù)據(jù)操作都在寄存器中完成；尋址方式靈活簡(jiǎn)單，執(zhí)行效率高；指令長(zhǎng)度固定；對(duì)操作系統(tǒng)的支持廣泛。4.1ARM處理器的應(yīng)用領(lǐng)域嵌入式控制汽車、電子設(shè)備、保安設(shè)備、大容量存儲(chǔ)器、調(diào)制解調(diào)器、打印機(jī)。數(shù)字消費(fèi)產(chǎn)品數(shù)碼相機(jī)、數(shù)字式電視機(jī)、游戲機(jī)、GPS、機(jī)頂盒、MP4。便攜式產(chǎn)品手提式計(jì)算機(jī)、移動(dòng)電話、PDA、靈巧電話網(wǎng)絡(luò)設(shè)備VOIP、Wireless、xDSL4.2ARM處理器的應(yīng)用產(chǎn)品LexmarkZ52ColorJetprinterSamsungML5100AJVC"Pixstar"GC-X1HPJornado820PsionRevoPlusHPCapShareSonyMZ-R90MiniDiscNokia8810NokiaMediamasterNintendo

Gameboy

AdvanceEricssonR380AlbaBushInternetTV3Com10/100PCINICIomegaHipZipDiamondMultimediaRio6005.1ARM

處理器系列

Processorcore ArchitectureARM7TDMIfamily v4TARM720T,ARM740TARM9TDMIfamily

v4TARM920T,ARM922T,ARM940TARM9Efamily v5TE,v5TEJARM946E-S,ARM966E-S,ARM926EJ-SARM10Efamily v5TE,v5TEJARM1020E,ARM1022E,ARM1026EJ-SARM11family v6ARM1136J(F)-S

v6ARM1156T2(F)-S

v6T2ARM1176JZ(F)-S

v6Z5.1ARM

處理器系列CortexMfamily

v7ARMCortex-M0

v7MARMCortex-M3

v7MARMCortex-M4

v7MCortexMfamily

v7ARMCortex-R4

v7RCortexAfamily

v7ARMCortex-A8

v7AARMCortex-A9

v7AARMCortex-A15

v7ACortexA50family

v7ARMCortex-A50 v8A5.2ARM7TDMIfamilyARM7TDMIfeatures3stagepipelineVonNeumannarchitectureCPI~1.9T Thumbinstructionsetsupport32-bitARMinstructions16-bitThumbinstructionsD DebugsupportM Enhancedmultiplier(32x8)withinstructionsfor64-bitresultsI EmbeddedICELogic5.2ARM7TDMIfamily－PipelineAlloperationshereareonregisters(singlecycleexecution)Inthisexampleittakes6clockcyclestoexecute6instructionsClockcyclesperInstruction(CPI)=1CycleOperationADDSUBORRANDEORORR123456789FDEFDEFEFDEFDEDFDEWF-Fetch D

-Decode E-ExecuteM5.3ARM9TDMIfamily5stagepipelineImprovesCPIto~1.5ImprovedmaximumclockfrequencyHarvardarchitectureIncreasesavailablememorybandwidthSimultaneousaccesstoinstructionanddatamemorycanbeachievedNormallysuppliedwithcachesattachedARM922T(pictured)2x8KcachesMemoryManagementUnit(MMU)WriteBufferARM920TAsARM922Tbutwith2x16KcachesARM940THasaMemoryProtectionUnit(MPU)5.3ARM9TDMIfamily－PipelineInstructionFetch

Shift+ALUMemoryAccessRegWriteRegReadRegDecodeFETCHDECODEEXECUTEMEMORYWRITEARM9TDMIARMorThumb

InstDecodeRegSelectRegReadShiftALURegWriteThumb?ARM

decompressARMdecodeInstructionFetchFETCHDECODEEXECUTEARM7TDMI5.4ARM9EfamilyARM9EisbasedontheARM9TDMIcoreCoreimplementationdifferencesArchitectureV5TEsupportSinglecycle32x16multiplierimplementationEmbeddedICELogicRTARM926EJ-S/ARM946E-SConfigurableInstructionandDatacachesInstructionandDataTCMInterfacesAHBbusinterfaceARM926EJ-ShasMMUARM946E-ShasMPUARM966E-SInstructionandDataTCMInterfacesNoCacheorMPU/MMU5.5ARM10EfamilyAnewimplementationoftheARMV5TEarchitectureLongerpipelineforgreaterinstructionthroughput64-bitmemoryinterfacesCorefeaturesArchitecturev5TECPI1.36stagepipelineStaticbranchprediction“Hitundermiss”supportNon-blockingexecutionunit64bitspercycleLDM/STMoperationsEmbeddedICELogicRT-II5.6ARM11family－ARM1136J-SARM1136JF-S(pictured)SynthesizableARMV6ArchitectureHighPerformanceCore8-stagepipelineStaticandDynamicbranchpredictionReturnstackLowlatencyInterruptModePhysically-tagged4-64kI&DCachesInternalConfigurableTCMsFourmainmemoryportsJazelletechnologyIntegratedVFPcoprocessorARM1136J-SAsabovebutwithnoVFP5.6ARM11family－ARM1156T2-SARM1156T2F-S(pictured)AsARM1136JF-SARMv6T2architectureBlended16/32-bitThumb-2Instructionset26%smallerthanARMcode25%fasterthanThumbcodeARM1156T2-SAsabovebutwithnoVFP5.6ARM11family－ARM1176JZ-SARM1176JZF-S(pictured)AsARM1136JF-SARMv6ZarchitectureTrustZonetechnologyParallel“Secureworld”forsensitiveapplicationsARM1176JZ-SAsabovebutwithnoVFP5.7Cortexfamily－M3SWDorJTAGFlashPatch&BreakpointsDataWatchpoints&TraceDebugandSleepControl3-StagePipeline,HarvardArchitecture,Thumb-2ISA(orThumb)30K*Gates1-240ConfigurableInterruptsConfigurablePriorityLevelsNonMaskableInterruptOptionalSerialWireViewer5.7Cortexfamily－M3ARMv7MArchitectureNoARMinstructionsetsupportThumb-2onlyNoCache-NoMMUDebugisoptimizedformicrocontrollerapplicationsVectortableisaddresses,notinstructionsInterruptsautomaticallysave/restorestateExceptionsprogrammedinCNoCoprocessor15Allregistersarememory-mappedInterruptcontrollerispartofCortex-M3macrocell5.7Cortexfamily－R4SynthesizableARMv7-RArchitectureDivideinstructionsSupportforMixedEndiannessUnaligneddatasupportv7DebugArchitectureHighPerformanceCore8-stagepipelineDynamicBranchpredictionReturnstackHardwareDivideNon-maskableinterruptoptionConfigurablecachesandTCMsWithexternalDMAsupport5.7Cortexfamily－A8ProcessorhighlightsHighfrequency,highefficiency,lowpowerIn-order,dual-i