ToolsSupports

(LVPECL)，低壓差分信號(LVDS)，或者低壓CMOS( S)對）325mm5mm3.3V

PCICDCM9102是一款為諸如PCIExpress?的通信標(biāo)準(zhǔn)提供基準(zhǔn)時(shí)鐘而設(shè)計(jì)的低抖動時(shí)鐘.該器件最高支持PCIE3代，易于配置和使用。CDCM9102提供2個(gè)100MHz差分時(shí)鐘端口。這些端口支持的輸出類型包括LVPECL，LVDS，或者一對LVCMOS緩沖個(gè)單端25MHz時(shí)鐘輸出端口。這一端口的使用包括通用計(jì)時(shí)、計(jì)時(shí)以太網(wǎng)物理層(PHY)、或者為附加的個(gè)單一外部25MHz晶體。VQFN5.00mmxHCSLHCSLHCSL471471100MHz150150?5656

Copyright?2016,TexasInstrumentsAnIMPORTANTNOTICEattheendofthisdatasheetaddressesavailability,warranty,changes,useinsafety-criticalapplications,inlectualpropertymattersandotherimportantdiers.PRODUCTIONDATA.EnglishDataSheet:特 應(yīng)用范 說 DeviceComparison PinConfigurationand Absoluteum ESD mendedOperating Thermal Timing ParameterMeasurement Test Detailed

FunctionalBlock DeviceFunctional Applicationand Power Thermal PowerSupply Layout Layout 靜電放 ChangesfromOriginal(February2012)toRevision 已添加文本至說明“該器件最高支持PCIE3代 Changedpartnumberto1134 Changedpartnumberto AddedtextandFigure16toPCIExpress DeviceComparison32-pinVQFN(RHB)package,smalltapeand–40°Cto32-pinVQFN(RHB)package,tapeandPinConfigurationand32-PinVQFN(Top 12345678 12345678PinPOWERThermalpad,14,GPowersupplygroundandthermalPCapacitorforinternalregulator,connect10-μFY5VcapacitortoPCapacitorforinternalregulator,connect10-μFY5Vcapacitorto4PPowerSupply,OUT0clock1PPowerSupply,OUT1clock9PPowersupply,low-noiseclockPPowersupply,low-noiseclockPPowersupply,low-noiseclockPPowersupply,crystaloscillatorG=Ground,I=Input,O=Output,P=PinFunctions(8,13,15,—Noconnection7OOutputenable/shutdowncontrolinput(seeTableOOutputformatselectcontrolinputs(seeTableOOutputformatselectcontrolinputs(seeTableIDeviceresetinput(active-low)(seeTableIParallelresonantcrystalinput(25DEVICEOOscillatoroutputport(255OOutput0–negativeterminal(1006OOutput0–positiveterminal(1002OOutput1–negativeterminal(1003OOutput1–positiveterminal(100Forproperdevicestartup,itis mendedthatacapacitorbeinstalledfrompin12toGND.SeeStart-UpTimeEstimationformoreAbsoluteumoveroperating-airtemperaturerange(unlessotherwiseInputOutputSupplyVInputVDDx+VOutputVDDx+VStressesbeyondthoselistedunderAbsoluteumRatingsmaycausepermanentdamagetothedevice.Thesearestressratingsonly,whichdonotimplyfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunder OperatingConditions.Exposuretoabsolute-um-ratedconditionsforextendedperiodsmayaffectdevicereliability.SupplyvoltagesmustbeappliedTheinputandoutputnegativevoltageratingsmaybeexceedediftheinputandoutputclamp–currentratingsareESDV(ESD)ElectrostaticV JEP155statesthat500-VHBMallowssafemanufacturingwithastandardESDcontrol JEP157statesthat250-VCDMallowssafemanufacturingwithastandardESDcontrolmendedOperating3VThermalRHB32Junction-to-case(top)thermalJunction-to-boardthermalJunction-to-topcharacterizationJunction-to-boardcharacterization2Junction-to-case(bottom)thermalFormoreinformationabouttraditionalandnewthermalmetrics,seetheSemiconductorandICPackageThermalMetricsapplicationreport,SPRA953.4×4ViasonElectricaloveroperating-airtemperaturerange(unlessotherwiseTESTInputhigh0.6×VInputlow0.4×VInputhighVDD=3.6V,VIL=0InputlowVDD=3V,VIH=3.6CInput8InputpullupCrystalinputΩCOn-chipload8umdrivelevel- umshunt7CLOCKOUTPUTBUFFER(OUTPUTMODE=OutputhighVDD–VDD–VOutputlowVDD–VDD–VVtRandOutputriseandfall20%toOutputdutySkewbetweenCLOCKOUTPUTBUFFER(OUTPUTMODE=VVODmagnitudeVVOSmagnitudetRandOutputriseandfall20%toOutputdutySkewbetweenCLOCKOUTPUTBUFFER(OUTPUTMODE=OutputhighVCC=3Vto3.6V,IOH=–100VDD–VOutputlowVCC=3Vto3.6V,IOH=100VOutputrise/fallslew20%toOutputdutySkewbetweenLVCMOSinputsatTA=–40°CtoCrystalcharacteristicsforexternal25MHzcrystalwithVDD=3.3V,TA=–40°CtoClockoutputbufferwithoutputmode=LVPECLatVDD1,VDD2=3.3V;TA=–40°CtoClockoutputbufferwithoutputmode=LVDSatVDD1,VDD2=3.3V;TA=–40°CtoClockoutputbufferwithoutputmode=LVCMOSatVDD1,VDD2=3.3V;TA=–40°CtoTimingfOUT=100MHz,VDD=3.3V,TA=25°C,andjitterintegrationbandwidthbetween10kHzand20MHz(unlessotherwise LVCMOSOUTPUTfsPeriodpspk-LVPECLOUTPUTfsPeriodpspk-LVDSOUTPUTfsPeriodpspk-TypicalFigure1.CDCM9102TypicalPhaseNoisePerformance(LVPECLParameterMeasurementTest5Figure2.LVCMOSOutputTest505050Phase Figure3.LVCMOSACConfigurationforDevice505050VDD-2Figure4.LVPECLDCConfigurationforDevice15015050Phase 50Figure5.LVPECLACConfigurationforDevice5010050100505050 Figure5050 505050Figure7.LVDSACConfigurationforDeviceDetailedTheCDCM9102isahigh-performancePLLthatgenerates2copiesofcommonly-usedreferenceclockswithlessthan1-psRMSjitterfromalow-costcrystal.FunctionalBlock OS1Copyright?2016,TexasInstrumentsFeatureTheCDCM9102includesanon-chipPLLwithanon-chipVCO.ThePLLblocksconsistofacrystalinputinterface,aphasefrequencydetector(PFD),achargepump,anon-chiploopfilter,andprescalerandfeedbackdividers.CompletingtheCDCM9102devicearetheoutputdivideranduniversaloutputbuffer.ThePLLandoutputdividerarepre-programmedtogenerate2copiesof100MHzinLVCMOS,LVPECLorLVDSformat.ThePLLispoweredbyon-chip,low-dropout(LDO)linearvoltageregulators.Theregulatedsupplynetworkispartitionedsuchthatthesensitive ogsarepoweredfromseparateLDOsratherthanthedigitalswhichuseaseparateLDOregulator.TheseLDOsprovideisolationforthePLLfromanynoiseintheexternalpower-supplyrail.TheREG_CAP1andREG_CAP2pinsshouldeachbeconnectedtogroundby10-capacitorstoensureDeviceFunctionalCrystalInput(XIN)TheCDCM9102implementsaColpittsoscillator;therefore,onesideofthecrystalconnectstotheXINpinandtheothercrystalterminalconnectstoground.Thedevicerequirestheuseofafundamental-modecrystal,andtheoscillatoroperatesinparallelresonancemode.Thecorrectloadcapacitanceisnecessarytoensurethatthecircuitoscillatesproperly.Theloadcapacitancecomprisesallcapacitancesintheoscillatorfeedbackloop(thecapacitancesseenbetweentheterminalsofthecrystalinthecircuit).ItisimportanttoaccountforallsourcesofcapacitancewhencalculatingthecorrectvaluefortheexternaldiscreteloadcapacitanceshowninFigure8.25Figure8.ConfigurationofCircuitforCDCM9102XINDeviceFunctionalModes(TheCDCM9102hasbeencharacterizedwith10-pFparallel-resonantcrystals.TheinputstageofthecrystaloscillatorintheCDCM9102isdesignedtooscillateatthecorrectfrequencyforallparallel-resonantcrystalswithlow-pullcapabilityandratedwithaloadcapacitancethatisequaltothesumoftheon-chiploadcapacitanceattheXINpin(CIN=10pFum),crystalstraycapacitance,andboardparasiticcapacitancebetweenthecrystalandXINpin.Tominimizestrayandparasiticcapacitances,minimizethetracedistanceroutedfromthecrystaltotheXINpinandavoidotheractivetracesandactivecircuitryintheareaofthecrystaloscillatorcircuit.Table1listscrystaltypesthathavebeenevaluatedwiththeCDCM9102.Table1.CDCM9102 PARTAmismatchoftheloadcapacitanceresultsinafrequencyerroraccordingtoEquationΔf f 2C+C +C

Δ?isthefrequencyerrorrequiredbythefisthefundamentalfrequencyoftheCSisthemotionalcapacitanceofthecrystal.ThisisaparameterinthedatasheetoftheC0istheshuntcapacitanceofthecrystal.ThisisaparameterinthedatasheetoftheCLristheratedloadcapacitanceofthecrystal.ThisisaparameterinthedatasheetoftheCLaistheactualloadcapacitanceimplementedonthePCB(CIN+straycapacitance+parasiticcapacitance+ Thedifferencebetweentheratedloadcapacitance(fromthecrystaldatasheet)andtheactualloadcapacitance(CLa=CIN+CL+CSTRAY+CPARASITIC)shouldbeminimized.Acrystalwithalowpullabilityrating(lowCS)isDesignDesiredfrequencytoleranceΔf≤±80ppmCrystalVendorParameters:IntrinsicFrequencyTolerance=±30ppmC0=7pF(shuntcapacitance)CS=10fF(motionalcapacitance)CLr=12pF(loadcapacitance)SubstitutingtheseparametersintoEquation1yieldsaumvalueofCLa=17pFtoachievethedesiredΔf(±50ppm).RecallthatCLa=CIN+CL+CSTRAY+CPARASITIC=8pF+(CL+CSTRAY+CPARASITIC).Ideally,theloadpresentedtothiscrystalshouldbe12pF;therefore,thesumof(CL+CSTRAY+CPARASITIC)mustbelessthan9pF.Strayandparasiticcapacitancemustbecontrolled.ThisisbecausetheColpittsoscillatorisparticularlysensitivetocapacitanceinparallelwiththecrystal;therefore,goodlayoutpracticeisessential.TI thatthedesignerextractthestrayandparasiticcapacitancefromtheprinted-circuitboarddesigntoolandadjustCLaccordinglytoachieveCLr=CLa.Incommonscenarios,theexternalloadcapacitorisoftenunnecessary;however,TI mendsthatpadsbeimplementedto modateanexternalloadcapacitorsothattheppmerrorcanbeminimized.CertainPCIExpressapplicationsrequireHCSLsignaling.Becausethecommon-modevoltageforLVPECLandHCSLaredifferent,applicationsrequiringHCSLsignalingmustuseAC-couplingasshowninFigure9.The150-ΩresistorsensureproperbiasingoftheCDCM9102LVPECLoutputstage.The471-Ωand56-ΩresistornetworkbiasestheHCSLreceiverinputstage.471150150

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CN=8pF(typical),10pF(um);seeElectricalFigure9.InterfacingBetweenLVPECLandTable2andTable3listthepincontrolsandpinconfigurationsoftheCDCM9102output.Table4liststhedeviceDeviceTable2.CDCM9102PinControlofOutputOE(PinDEVICE0PowerPower1Table3.CDCM9102PinConfigurationofOutputCONTROLOUTPUTOS1(PinOS0(Pin00LVCMOS,OSCOUT=01LVDS,OSCOUT=10LVPECL,OSCOUT=11LVPECL,OSCOUT=Table4.CDCM9102DeviceRESET(PinDEVICE0Device0→1ApplicationandInformationinthefollowingapplicationssectionsisnotpartoftheTIcomponentspecification,andTIdoesnotwarrantitsaccuracyorcompleteness.TI’scustomersareresponsiblefordeterminingsuitabilityofcomponentsfortheirpurposes.Customersshouldvalidateandtesttheirdesignimplementationtoconfirmsystemfunctionality.ApplicationStart-UpTimeTheCDCM9102containsalow-noiseclockgeneratorthatcalibratestoanoptimaloperatingpointatdevicepowerup.Toensureproperdeviceoperation,theoscillatormustbestablebeforethelow-noiseclockgeneratorcalibrationprocedure.Quartz-basedoscillatorscantakeupto2mstostabilize;therefore,TI mendsthattheapplicationensurethattheRESETpinisde-assertedatleast5msafterthepowersupplyhasfinishedram.Thiscanbe plishedbycontrollingtheRESETpindirectly,orbyapplyinga47-nFcapacitortogroundontheRESETpin(thisprovidesadelaybecausetheRESETpinincludesa150-kΩpullupresistor.TheCDCM9102start-uptimecanbeestimatedbasedonparametersdefinedinTable5andgraphicallyshowninFigure10.Table5.CDCM9102Start-UpTimeFORMULAORMETHODOFReferenceclockThereciprocaloftheappliedreferencefrequencyinseconds1tREF= =0.04Power-upime(lowPower-supplyrisetimetolowlimitofpower-on-resettrippointTimerequiredforpowersupplytorampto2.27Power-upime(highPowersupplyrisetimetohighlimitofpower-on-resettrippointTimerequiredforpowersupplytorampto2.64Referencestart-upAfterPORreleases,theColpittsoscillatorisenabled.Thisstart-uptimeisrequiredfortheoscillatortogenerateherequisitesignallevelsforthedelayblocktobeclockedbythereferenceinput.500μsbestcaseand800μsworstcase(foracrystalDelayInternaldelaytimegeneratedfromthereferenceclock.Thisdelayprovidesimeforthereferenceoscillatortostabilize.tdelay=16,384×tREF=655VCOcalibrationVCOcalibrationtimegeneratedfromthereferenceclock.ThisprocessselectstheoperatingpointfortheVCObasedonthePLLsetings.tVCO_CAL=550×tREF=22PLLlockTimerequriedforPLLtolockwihin±10ppmoffREFThePLLsettlesin12.5VCO PLLtPLLtVCOTime-PowerPowerSupply-Figure10.CDCM9102Start-UpTimeTheCDCM9102start-uptimelimits,tMAXandtMIN,cannowbecalculatedwithEquation2andEquationtMAX=tpuh+trsu+tdelay+tVCO_CAL+ tMIN=tpul+trsu+tdelay+tVCO_CAL+ OutputTheCDCM9102isa3.3-Vclockdriverwhichhasthefollowingoptionsfortheoutputtype:LVPECL,LVDS,andLVPECLTheCDCM9102isanopenemitterforLVPECLoutputs.Therefore,properbiasingandterminationisrequiredtoensurecorrectoperationofthedeviceandtooptimizesignalintegrity.TheproperterminationforLVPECLis50Ωto(Vcc-2)VbutthisDCvoltageisnotreadilyavailableonaboard.ThusaThevenin’sequivalentcircuitisworkedoutfortheLVPECLterminationinbothdirect-coupled(DC)andAC-coupledcases,asshowninFigure11andFigure12.TI mendscingallresistivecomponentsclosetoeitherthedriverendorthereceiverend.Ifthesupplyvoltagesofthedriverandreceiveraredifferent,ACcouplingisrequired.130

82

Figure11.LVPECLOutputTermination(DC-15015050Figure12.LVPECLOutputTermination(AC-LVDSTheproperLVDSterminationforsignalintegrityovertwo50-Ωlinesis100Ωbetweentheoutputsonthereceiverend.Eitheradirect-coupled(dc)terminationorac-coupledterminationcanbeusedforLVDSoutputs,asshowninFigure13andFigure14.TI mendscingallresistivecomponentsclosetoeitherthedriverendorthereceiverend.Ifthesupplyvoltagesofthedriverandreceiveraredifferent,ACcouplingisrequired. Figure13.LVDSOutputTermination(DC100100Figure14.LVDSOutputTermination(ACLVCMOSSeriesterminationisacommonmethodtomaintainthesignalintegrityforLVCMOSdrivers,ifconnectedtoareceiverwithahigh-impedanceinput.Forseriestermination,aseriesresistor,Rs,iscedclosetothedriver,asshowninFigure15.ThesumofthedriverimpedanceandRsshouldbeclosetothetransmission-lineimpedance,whichisusually50Ω.BecausetheLVCMOSdriverintheCDCM9102hasanimpedanceof30Ω,mendsRsbe22Ωtomaintainpropersignal Figure15.LVCMOSOutputPCIExpressTexasInstrumentsoffersacompleteclocksolutionforPCIExpressapplications.TheCDCUN1208LPcanbeusedtofanoutreferenceclockgeneratedbytheCDCM9102asshowninFigure16.100MHz HCSLHCSLUpto8x

Figure16.ClockSolutionforPCIEExpressTypical2525

100Copyright?2016,TexasInstrumentsFigure17.CDCM9102TypicalApplicationDesignConsideratypicalwiredcommunicationsapplication,likeatop-of-rackswitch,whichneedstoclockPCIExpressGen2or3PHYs.Forsuchasynchronoussystems,thereferenceinputcanbeacrystal.Insuchsystems,theclocksareexpectedtobeavailableuponpowerupwithouttheneedforanydevice-levelprogramming.Anexampleofclockinputandoutputrequirementsisshownbelow:Clock25-MHzClock2×100MHzclockforPCIExpressGen3(8GT/s),SeeDetailedDesignProcedureforhowtogeneratetherequiredoutputfrequenciesforthisapplicationusingtheTypicalApplication(DetailedDesignDesignofallaspectsoftheCDCM61004isquiteinvolvedandsoftwaresupportisavailabletoassistinpartselectionandphasenoisesimulation.Thisdesignprocedurewillgiveaquickoutlineoftheprocess.DeviceThefirststepistocalculatetheVCOfrequencygiventherequiredoutputfrequency.ThedevicemustbeabletoproducetheVCOfrequencythatcanbedivideddowntotherequiredoutputfrequency.TheWEBENCHClockArchitectToolfromTIwillaidintheselectionoftherightdevicethatmeetsthecustomer'soutputfrequenciesandformatrequirements.DeviceTheWEBENCHClockArchitectToolattemptsto izethephasedetectorfrequency,usesmallestdividers,and izesPLLbandwidth.DeviceUsetheWEBENCHClockArchitectTool.Entertherequiredfrequenciesandformatsintothetool.Tousethisdevice,findasolutionusingtheCDCM9102.CalculationUsingInthisexample,thevalidVCOfrequencyforCDCM9102is1.8DeviceForthisexample,whenusingtheWEBENCHClockArchitectTool,thereferencewouldhavebeenmanuallyenteredas25MHzaccordingtoinputfrequencyrequirements.EnterthedesiredoutputfrequenciesandclickonGenerateSolutions.SelectCDCM9102fromthesolutionlist.FromthesimulationpageoftheWEBENCHClockArchitectTool,itcanbeseenthatto izephasedetectorfrequencies,theNdividerissetto24andprescalerdividerissetto3.ThisresultsinaVCOfrequencyof1.8GHz.Theoutputdividerissetto6.Atthispointthedesignmeetsallinputandoutputfrequencyrequirementsandsimulateperformanceontheclockoutputs.Figure18showsthetypicalphasenoiseplotofthe100MHzLVPECLoutput.TypicalApplication(ApplicationFigure18.TypicalPhaseNoisePlotof100MHzLVPECLPower TA=–40°Cto85°C,VDDx=3.3V,OE=1,valuesrepresentcumulativecurrent/poweronallVDDxTable6.DeviceCurrentcorecurrentOutputV×?out×(CL+20×10–12)×V2×?out×(CL+20×10–12)×ThermalToensureoptimalperformanceandreliability,goodthermaldesignpracticesareimportantwhenusingtheCDCM9102.Dietemperatureshouldbelimitedtoa umof125°C.Thatis,asanestimate,TA(ambienttemperature)plusdevicepowerconsumptiontimesRθJAshouldnotexceed125°C.5.00.33mm,Thedevicepackagehasanexposedpadthatprovidestheprimaryheatremovalpathaswellasanelectricalgroundingtotheprintedcircuitboard(PCB).To izetheremovalofheatfromthepackage,athermallandingpatternincludingmultipleviastoagroundnemustbeincorporatedonthePCBwithinthefootprintofthepackage.Theexposedpadmustbesoldereddowntoensureadequateheatconductionoutofthepackage.5.00.33mm,mm,Figure mendedPCBLayoutforPowerSupplyPLL-basedfrequencysynthesizersareverysensitivetonoiseonthepowersupply,whichcandramaticallyincreasethejitterofthePLL.Thisisespeciallytrueforog-basedPLLs.Thus,itisessentialtoreducenoisefromthesystempowersupply,especiallywhenjitter/phasenoiseisverycriticaltoapplications.APLLhasattenuatedjitterduetopowersupplynoiseatfrequenciesbeyondthePLLbandwidthduetoattenuationbytheloopresponse.Filtercapacitorsareusedtoeliminatethelow-frequencynoisefromthepowersupply,wherethebypasscapacitorsprovidetheverylow-impedancepathforhigh-frequencynoiseandguardthepowersupplysystemagainstinducedfluctuations.Thebypasscapacitorsalsoprovideasourceofinstantaneouscurrentasrequiredbythedeviceoutputstages.Therefore,bypasscapacitorsmusthavelowESR.Toproperlyusethebypasscapacitors,theymustbecedveryclosetothepowersupplypinsandmustbelaidoutwithshortloopstominimizeinductance.Figure20showsageneral mendationfordecouplingthepowersupply.TheCDCXM9102powersfallintooneoftwocategories: s(VDD3,VDD4,andVDD5),andinput/outputs(VDD1,VDD2,andVDD6).Shortthe stogethertoformthe ogsupplynode;likewise,shorttheinput/outputstogethertoformtheI/Osupplynode.Isolatethe ognodefromthePCBpowersupplyandI/Onodebyinsertingaferritebead.Thishelpsisolatethehigh-frequencyswitchingnoisesgeneratedbytheclockdriversandI/Ofromthesensitive ogsupplynode.Choosinganappropriateferritebeadwithlowdcisimportant,asitisimperativetomaintainavoltageatthepower-supplypinoftheCDCM9102thatisovertheminimumvoltageneededforitsproperPowerSupplyFiltering(og0.1 Figure20.CDCM9102PowerSupplyDecoupling–PowerPinBypassLayoutTheCDCM9102isahigh-performancedevice;therefore,paycarefulattentiontodeviceconfigurationandprinted-circuitboardlayoutwithrespecttopowerconsumption.Observinggoodthermallayoutpracticesenablesthethermalpadonthebacksideofthe32-pinVQFNpackagetoprovideagoodthermalpathbetweenthediecontainedwithinthepackageandtheambientair.Thisthermalpadalsoservesasthegroundconnectionthedevice;therefore,alowinductanceconnectiontothegroundneisessential.LayoutFigure21showsageneral mendationofPCBlayoutwiththeCDCM9102thatensuresgoodsystem-levelthermalreliability.Back Component ThermalSolder Thermal

NoSolder

Figure mendedPCB

Pad(backside)ThefollowinglinksconnecttoTIcommunityresources.Linkedcontentsareprovided"ASIS"bytherespectivecontributors.TheydonotconstituteTIspecificationsanddonotnecessarilyreflectTI'sviews;seeTI'sTermsofTIE2E?OnlineCommunityTI'sEngineer-to-Engineer(E2E)Community.Createdtofostercollaborationamongengineers.At ,youcanaskquestions,shareknowledge,exploreideasandhelpsolveproblemswithfellowengineers.DesignSupportTI'sDesignSupportQuicklyfindhelpfulE2Eforumsalongwithdesignsupporttoolsandcontactinformationfortechnicalsupport.E2EisatrademarkofTexasInstruments.PCIExpressisatrademarkofPCI-SIG.AllothertrademarksarethepropertyoftheirrespectiveSLYZ022—TIThisglossarylistsandexinsterms,acronyms,and?2012–2016,TexasInstruments 德州儀器(TI)及其下屬子公司有權(quán)根據(jù)JESD46標(biāo)準(zhǔn),對所提供的產(chǎn)品和服務(wù)進(jìn)行更正、修改、增強(qiáng)、改進(jìn)或其它更改，并有權(quán)根據(jù)JESD48標(biāo)準(zhǔn)中止提供任何產(chǎn)品和服務(wù)。客戶在下訂單前應(yīng)獲取的相關(guān)信息,并驗(yàn)證這些信息是否完整且是的。所有產(chǎn)品的銷售都遵循在訂單確認(rèn)時(shí)所提供的TI銷售條款與條件。用測試或其它質(zhì)量控制技術(shù)。除非適用法律做出了硬性規(guī)定，否則沒有必要對每種組件的所有參數(shù)進(jìn)試。TI不對任何TI專利權(quán)、、作品權(quán)或其它與使用了TI組件或服務(wù)的組合設(shè)備、機(jī)器或流程相關(guān)的TI知識中授予的直接或隱含權(quán)限作出任何保證或解釋。TI所發(fā)布的與第產(chǎn)品或服務(wù)有關(guān)的信息，不能構(gòu)成從TI獲得使用這些產(chǎn)品或服務(wù)的、、或認(rèn)可。使用此類信息可能需要獲得第的專利權(quán)或其它知識方面的，或是TI的專利權(quán)或其它知識方面的。。TI對此類篡改過的文件不承擔(dān)任何責(zé)任或義務(wù)。第的信息可能需要服從額外的限制條件。示或暗示，且這是不正當(dāng)?shù)摹⑿陨虡I(yè)行為。TI對任何此類虛假陳述均不承擔(dān)任何責(zé)任或義務(wù)。律、和安全相關(guān)要求?？蛻舨⑼?，他們具備制定與實(shí)施安全措施所需的全部專業(yè)技術(shù)和知識，可預(yù)見故障的、監(jiān)測故障TI組件而對TI及其造成的任何損失。TI法律和要求。 放大器和線 DLP?產(chǎn)品 RFID郵寄地址：市浦東新區(qū)世紀(jì)大道1568號，中建 32樓 Copyright?2016,德州儀器半導(dǎo)體技術(shù)（ PACKAGEOPTIONPACKAGINGOrderablePackageEcoMSLPeakOpTempDevice&noSb/Br)CU-40to&noSb/Br)CU-40to(1)ThemarketingstatusvaluesaredefinedasACTIVE:Product mendedfornewLIFEBUY:TIhasannouncedthatthedevicewillbedis,andalifetime-buyperiodisin mendedfornewdesigns.Deviceisinproductiontosupportexistingcustomers,butTIdoes mendusingthispartinanewPREVIEW:Devicehasbeenannouncedbutisnotinproduction.SamplesmayormaynotbeOBSOLETE:TIhasdistheproductionofthe(2)Econ-Thennedeco-friendlyclassification:Pb-(RoHS),Pb-(RoHSExempt),orGreen(RoHS&noSb/Br)-pleasecheck informationandadditionalproductcontentdetails.TBD:ThePb-/Green nhasnotbeenPb-(RoHS):TI'sterms"Lead- "or"Pb-"meansemiconductorproductsthatarecompatiblewiththecurrentRoHSrequirementsforall6substances,includingtherequirementthatleadnotexceed0.1%byweightinhomogeneousmaterials.Wheredesignedtobesolderedathightemperatures,TIPb-productsaresuitableforuseinspecifiedlead-processes.Pb-(RoHSExempt):ThiscomponenthasaRoHSexemptionforeither1)lead-basedflip-chipsolderbumpsusedbetweenthedieandpackage,or2)lead-baseddieadhesiveusedbetweenthedieandleadframe.ThecomponentisotherwiseconsideredPb-(RoHScompatible)asdefinedabove.Green(RoHS&noSb/Br):TIdefines"Green"tomeanPb-(RoHScompatble),andofBromine(Br)andAntimony(Sb)basedflameretardants(BrorSbdonotexceed0.1%byweightinhomogeneousmaterial)(3)MSL,PeakTemp.-TheMoistureSensitivityLevelratingaccordingtotheJEDECindustrystandardclassifications,andpeaksolder(4)Theremaybeadditionalmarking,whichrelatestothelogo,thelottracecodeinformation,ortheenvironmentalcategoryonthe(5)MultipleDeviceMarkingswillbeinsideparentheses.OnlyoneDeviceMarkingcontainedinparenthesesandseparatedbya"~"willappearonadevice.Ifalineisindentedthenitisacon