計算機組成原理

雙語教學(xué)課件WilliamStallings

ComputerOrganization

andArchitecture

6thEditionChapter

7Input/OutputInput/OutputProblemsWidevarietyofperipheralsDeliveringdifferentamountsofdataAtdifferentspeedsIndifferentformatsAllslowerthanCPUandRAMNeedI/OmodulesInput/OutputModuleInterfacetoCPUandMemoryInterfacetooneormoreperipheralsGenericModelofI/OModuleExternalDevicesHumanreadableScreen,printer,keyboardMachinereadableMonitoringandcontrolCommunicationModemNetworkInterfaceCard(NIC)ExternalDeviceBlockDiagramTypicalI/ODataRatesI/OModuleFunctionControl&TimingCPUCommunicationDeviceCommunicationDataBufferingErrorDetectionI/OStepse.g.ReadfrominputmoduleCPUchecksI/OmoduledevicestatusI/OmodulepreparesstatusforCPUtofetchIfthestatusisready,CPUrequestsdatatransferI/OmodulegetsdatafromdeviceCPUfetchesdatafromI/OmoduleVariationsforoutput,…I/OModuleDiagramI/OModuleDecisionsHideorrevealdevicepropertiestoCPUSupportmultipleorsingledeviceControldevicefunctionsorleaveforCPUAlsoO/Sdecisionse.g.UnixtreatseverythingitcanasafileInputOutputTechniquesProgrammedInterruptdrivenDirectMemoryAccess(DMA)ProgrammedI/OCPUhasdirectcontroloverI/OSensingstatusRead/writecommandsTransferringdataCPUwaitsforI/OmoduletocompleteoperationWastesCPUtimeProgrammedI/O-detailCPUrequestsI/OoperationI/OmoduleperformsoperationI/OmodulesetsstatusbitsCPUchecksstatusbitsperiodicallyI/OmoduledoesnotinformCPUdirectlyI/OmoduledoesnotinterruptCPUCPUmaywaitorcomebacklaterProgramI/OblockofdataPAGE206

IssuereadcommandtoI/OmoduleReadstatusofI/OmoduleCheckstatusReadwordfromI/OmoduleWritewordintomemoryDone?Nextinstruction

yesNoNoreadyreadyCPU->I/OI/O->CPUErrorConditionI/O->CPUCPU->MEMORYI/OCommandsCPUissuesaddressIdentifiesmodule(&deviceif>1permodule)CPUissuescommandControl-tellingmodulewhattodoe.g.spinupdiskTest-checkstatuse.g.power?Error?Read/WriteModuletransfersdataviabufferfrom/todeviceAddressingI/ODevicesUnderprogrammedI/Odatatransferisverylikememoryaccess(CPUviewpoint)EachdevicegivenuniqueidentifierCPUcommandscontainidentifier(address)I/OMappingMemorymappedI/ODevicesandmemoryshareanaddressspaceI/Olooksjustlikememoryread/writeNospecialcommandsforI/OLargeselectionofmemoryaccesscommandsavailableIsolatedI/OSeparateaddressspacesNeedI/OormemoryselectlinesSpecialcommandsforI/OLimitedset§7.4InterruptDrivenI/OPAGE208OvercomesCPUwaitingNorepeatedCPUcheckingofdeviceI/OmoduleinterruptswhenreadyTransferofControlviaInterruptspage61suspendingresumingbranchingprocessingInterrupt-drivenI/OblockofdataPAGE208

IssuereadcommandtoI/OmoduleReadstatusofI/OmoduleCheckstatusReadwordfromI/OmoduleWritewordintomemoryDone?Nextinstruction

yesNoreadyCPU->I/OI/O->CPUErrorConditionI/O->CPUCPU->MEMORYDosomethingelseinterruptSimpleinterruptprocessing

Hardware

softwareISRDevicecontrollerorothersystemhardwareissueaninterruptProcessorfinishesexecutionofcurrentinstructionProcessorsignalsacknowledgmentofinterruptProcessorpushesPSW&PContocontrolstackProcessorloadsnewPCvaluebasedoninterruptSaveremainderofprocessstateinformationProcessinterruptRestoreprocessstateinformationRestoreoldPSW&PCInterruptDrivenI/O

BasicOperationCPUissuesreadcommandI/OmodulegetsdatafromperipheralwhilstCPUdoesotherworkI/OmoduleinterruptsCPUCPUrequestsdataCPUfetchesdatafromI/OmoduleCPUViewpointIssuereadcommandDootherworkCheckforinterruptatendofeachinstructioncycleIfinterrupted:-Savecontext(registers)ProcessinterruptFetchdata&storeSeeOperatingSystemsnotesInterruptprocessing(1)0.CPUdoessomethingelse….1.ThedeviceissuesaninterruptsignaltoCPU2.TheCPUfinishesexecutionofthecurrentinstructionbeforerespondingtotheinterrupt3.TheCPUtestsfor&makessureofaninterrupt,andsendsanacknowledgesignaltodevice(allowsthedevicetoremoveitsinterruptsignal&tosendsinterruptnumbertoCPU)4.TheCPUsavesinformationofcurrentprogramtostackforresumingit.TheimportantinformationisPSW(runningstatusofcurrentprogram)&PC(theaddressofnextinstruction)Interruptprocessing(2)5.TheCPUloadsPCwiththeentrylocationofISR(InterruptServiceRoutine)whichrespondstothisinterrupt.TheCPUmustdeterminetheenterlocation(startaddress)ofISRbysomemethodbasedoninterruptnumber.AboveiscompletedbyHARDWAREintheinterruptcycle.FollowingiscompletedbySOFTWARE(ISR)6.TheCPUbeginstoexecutetheinstructionsofISR.Itsavestheremainder(thecontextofsomeregisters)ofprogram-interruptedontostackforresuming….(e.g.ACcontainsthesumofaddition…..)Interruptprocessing(3)7.TheCPUexecutesinstructionsofISRtoprocessinterrupt:testsstatusofdevice,fetchesdatafromthedevice,storesdatatomemory,….(orfetchesdataformmemory,sendsdatatodevice).8.Afterservice,theCPUpreparestoresumetheprogram-interrupted,CPUretrievestheremainderfromstack&restoresthemtoregisters.9.TheCPUexecutesthelastinstructionRETI(meansreturnfrominterrupt),theprocessingisrestoringPSW&PCfromstack.Interruptprocessing(4)10.Theinstructioncycle,theCPUfetchestheinstructionofprogram-interruptedbyPC&resumestheprogram-interrupted.DesignIssuesHowdoyouidentifythemoduleissuingtheinterrupt?Howdoyoudealwithmultipleinterrupts?i.e.aninterrupthandlerbeinginterruptedIdentifyingInterruptingModule(1)DifferentlineforeachmodulePCLimitsnumberofdevicesSoftwarepollCPUaskseachmoduleinturnSlowIdentifyingInterruptingModule(2)DaisyChainorHardwarepollInterruptAcknowledgesentdownachainModuleresponsibleplacesvectoronbusCPUusesvectortoidentifyhandlerroutineBusMasterModulemustclaimthebusbeforeitcanraiseinterrupte.g.PCI&SCSIMultipleInterruptsEachinterruptlinehasapriorityHigherprioritylinescaninterruptlowerprioritylinesIfbusmasteringonlycurrentmastercaninterruptExample-PCBus80x86hasoneinterruptline8086basedsystemsuseone8259Ainterruptcontroller8259Ahas8interruptlinesSequenceofEvents8259Aacceptsinterrupts8259Adeterminespriority8259Asignals8086(raisesINTRline)CPUAcknowledges8259AputscorrectvectorondatabusCPUprocessesinterruptISABusInterruptSystemISAbuschainstwo8259AstogetherLinkisviainterrupt2Gives15lines16lineslessoneforlinkIRQ9isusedtore-routeanythingtryingtouseIRQ2BackwardscompatibilityIncorporatedinchipset82C59AInterrupt

ControllerIntel82C55A

ProgrammablePeripheralInterfaceUsing82C55AToControlKeyboard/Display§7.5DirectMemoryAccesspage216InterruptdrivenandprogrammedI/OrequireactiveCPUinterventionTransferrateislimitedCPUistiedupDMAistheanswerDMAFunctionAdditionalModule(hardware)onbusDMAcontrollertakesoverfromCPUforI/ODMAModuleDiagramDMAOperationCPUtellsDMAcontroller:Read/WriteDeviceaddressStartingaddressofmemoryblockfordataAmountofdatatobetransferredCPUcarriesonwithotherworkDMAcontrollerdealswithtransferDMAcontrollersendsinterruptwhenfinishedDMATransfer

CycleStealingDMAcontrollertakesoverbusforacycleTransferofonewordofdataNotaninterruptCPUdoesnotswitchcontextCPUsuspendedjustbeforeitaccessesbusi.e.beforeanoperandordatafetchoradatawriteSlowsdownCPUbutnotasmuchasCPUdoingtransferAsideWhateffectdoescachingmemoryhaveonDMA?Hint:howmucharethesystembusesavailable?DMAConfigurations(1)SingleBus,DetachedDMAcontrollerEachtransferusesbustwiceI/OtoDMAthenDMAtomemoryCPUissuspendedtwiceDMAConfigurations(2)SingleBus,IntegratedDMAcontrollerControllermaysupport>1deviceEachtransferusesbusonceDMAtomemoryCPUissuspendedonceDMAConfigurations(3)SeparateI/OBusBussupportsallDMAenableddevicesEachtransferusesbusonceDMAtomemoryCPUissuspendedonceI/OChannelsI/Odevicesgettingmoresophisticatede.g.3DgraphicscardsCPUinstructsI/OcontrollertodotransferI/OcontrollerdoesentiretransferImprovesspeedTakesloadoffCPUDedicatedprocessorisfasterI/OChannelArchitectureInterfacingConnectingdevicestogetherBitofwire?Dedicatedprocessor/memory/buses?E.g.FireWire,InfiniBandIEEE1394FireWireHighperformanceserialbusFastLowcostEasytoimplementAlsobeingusedindigitalcameras,VCRsandTVFireWireConfigurationDaisychainUpto63devicesonsingleportReally64ofwhichoneistheinterfaceitselfUpto1022busescanbeconnectedwithbridgesAutomaticconfigurationNobusterminatorsMaybetreestructureSimpleFireWireConfigurationFireWire3LayerStackPhysicalTransmissionmedium,electricalandsignalingcharacteristicsLinkTransmissionofdatainpacketsTransactionRequest-responseprotocolFireWireProtocolStackFireWire-PhysicalLayerDataratesfrom25to400MbpsTwoformsofarbitrationBasedontreestructureRootactsasarbiterFirstcomefirstservedNaturalprioritycontrolssimultaneousrequestsi.e.whoisnearesttorootFairarbitrationUrgentarbitrationFireWire-LinkLayerTwotransmissiontypesAsynchronousVariableamountofdataandseveralbytesoftransactiondatatransferredasapacketToexplicitaddressAcknowledgementreturnedIsochronousVariableamountofdatainsequenceoffixedsizepacketsatregularintervalsSimplifiedaddressingNoacknowledgementFireWireSubactionsInfiniBand