PAGEPAGE1 西華大學(xué)實(shí)驗(yàn)報告第組.第組實(shí)驗(yàn)報告（計算機(jī)類）開課學(xué)院及實(shí)驗(yàn)室：實(shí)驗(yàn)時間：年月日學(xué)生姓名學(xué)號成績學(xué)生所在學(xué)院年級/專業(yè)/班課程名稱EDA技術(shù)（機(jī)械）課程代碼實(shí)驗(yàn)項(xiàng)目名稱能自啟的七進(jìn)制計數(shù)器項(xiàng)目代碼指導(dǎo)教師項(xiàng)目學(xué)分一、實(shí)驗(yàn)?zāi)康?.了解VHDL語言編程方法，學(xué)會熟練運(yùn)用quartus軟件2.了解如何使用狀態(tài)機(jī)方法設(shè)計十三進(jìn)制計數(shù)器二、內(nèi)容與設(shè)計思想1.能自啟的七進(jìn)制計數(shù)器的狀態(tài)轉(zhuǎn)換圖101010100001/0/0 /0101010100001/1/0111110011/0/0111110011 2.能自啟的七進(jìn)制計數(shù)器引腳圖三、使用環(huán)境winXP或win7Quartusii編程環(huán)境核心代碼及調(diào)試過程能自啟動的七進(jìn)制計數(shù)器libraryieee;useieee.std_logic_1164.all;useieee.std_logic_arith.all;useieee.std_logic_unsigned.all;entityh34is port(cp:instd_logic;clocksignal q:outstd_logic_vector(2downto0);stateoutput y:outstd_logiccarryoutput );endh34;architecturewofh34istypestateisarray(2downto0)ofstd_logic;constants0:state:="001";constants1:state:="100";constants2:state:="010";constants3:state:="101";constants4:state:="110";constants5:state:="111";constants6:state:="011";signalp:state;signaln:state;begin s:process(cp) begin ifcp'eventandcp='1'then p<=n; endif; endprocesss; m:process(p) begin casepis whens0=>n<=s1; y<='0'; q<="100"; whens1=>n<=s2; y<='0'; q<="010"; whens2=>n<=s3; y<='0'; q<="101"; whens3=>n<=s4; y<='0'; q<="110"; whens4=>n<=s5; y<='0'; q<="111"; whens5=>n<=s6; y<='0'; q<="011"; whens6=>n<=s0; y<='1';