1、1,Chapter 6 Combinational Logic Design Practices(組合邏輯設(shè)計實踐),Documentation Standard and Circuit Timing (文檔標(biāo)準(zhǔn)和電路定時) Commonly Used MSI Combinational Logic Device (常用的中規(guī)模組合邏輯器件),Digital Logic Design and Application (數(shù)字邏輯設(shè)計及應(yīng)用),2,Review of Last Class (內(nèi)容回顧),6.1 Documentation Standard (文檔標(biāo)準(zhǔn)) Signal Name an

2、d Active Level (信號名和有效電平) Bubble-to-Bubble Logic Design (“圈到圈”邏輯設(shè)計),Digital Logic Design and Application (數(shù)字邏輯設(shè)計及應(yīng)用),3,6.2 Circuit Timing (電路定時) Propagation Delay (傳播延遲) Timing Analysis (定時分析) Timing Diagram (定時圖),Review of Last Class (內(nèi)容回顧),Digital Logic Design and Application (數(shù)字邏輯設(shè)計及應(yīng)用),4,開關(guān)狀態(tài)：1閉

3、合、0斷開 燈的狀態(tài)：1亮 、0不亮,邏輯與：當(dāng)且僅當(dāng)所有輸入條件都有效時，輸出狀態(tài)才有效。,開關(guān)狀態(tài)：0閉合、1斷開 燈的狀態(tài)：0亮 、1不亮,F = A + B = ( A B ),Review of Last Class (內(nèi)容回顧),Digital Logic Design and Application (數(shù)字邏輯設(shè)計及應(yīng)用),5,開關(guān)的有效狀態(tài)：閉合 燈的有效狀態(tài)：亮,有反相圈的引腳 表示低電平有效,給定邏輯功能只在符號框的內(nèi)部發(fā)生,Review of Last Class (內(nèi)容回顧),Digital Logic Design and Application (數(shù)字邏輯設(shè)計及應(yīng)用

4、),6,Decoders (譯碼器) Encoders (編碼器) Multiplexers (多路復(fù)用器) Parity Circuits (奇偶校驗) Comparators (比較器) Adders (加法器),Commonly Used MSI Combinational Logic Device(常用中規(guī)模組合邏輯器件）,Input Code Word,Output Code Word,Digital Logic Design and Application (數(shù)字邏輯設(shè)計及應(yīng)用),7,6.4 Decoder（譯碼器）,Binary Decoder (二進(jìn)制譯碼器),Yi = EN

5、mi,當(dāng)使能端有效時 Yi = mi,Truth Table for a 2-to-4 Binary Decoder,Digital Logic Design and Application (數(shù)字邏輯設(shè)計及應(yīng)用),8,The 74x139 Dual 2-to-4 Decoder(雙2-4譯碼器74x139),74x139,1 X X 1 1 1 1 0 0 0 1 1 1 0 0 0 1 1 1 0 1 0 1 0 1 0 1 1 0 1 1 0 1 1 1,Truth Table for One-half of a 74x139 Dual 2-to-4 Decoder,9,74x139,D

6、igital Logic Design and Application (數(shù)字邏輯設(shè)計及應(yīng)用),10,Yi = EN mi,Yi_L = Yi = ( EN mi ),EN = G1 G2A G2B = G1 G2A_L G2B_L,Digital Logic Design and Application (數(shù)字邏輯設(shè)計及應(yīng)用),11,用74x138設(shè)計4-16譯碼器,思路： 16個輸出需要 片74x138？,任何時刻只有一片在工作。 4個輸入中， 哪些位控制片選 哪些位控制輸入,Cascading Binary Decoders (級聯(lián)二進(jìn)制譯碼器）,12,Consider: How to

7、make a 5-to-32 Decoder with 3-to-8 Decoder? (思考：用74x138設(shè)計 5-32 譯碼器) How many 74x138 chips to be used with 32 outputs? (32個輸出需要多少片74x138 ？) Control that only one chip works in any time (控制任何時刻只有一片工作) Use the Enable Inputs (利用使能端),Digital Logic Design and Application (數(shù)字邏輯設(shè)計及應(yīng)用),13,Consider: How to ma

8、ke a 5-to-32 Decoder with 3-to-8 Decoder? (思考：用74x138設(shè)計 5-32 譯碼器),Control inputs of three low-order bits of a 5-bit code word (5個輸入的低3位控制輸入) Control chips of two high-order bits of a 5-bit code word (5個輸入的高2位控制片選) Use 2-to-4 Decoder ( 利用 2-4 譯碼器),Figure 6-37,Digital Logic Design and Application (數(shù)字邏

9、輯設(shè)計及應(yīng)用),14,補(bǔ)充：用譯碼器和邏輯門實現(xiàn)邏輯函數(shù),F = (X,Y,Z) (0,3,6,7) = (X,Y,Z) (1,2,4,5),對于二進(jìn)制譯碼器：Yi = EN mi 當(dāng)使能端有效時，Yi = mi 對低電平有效輸出：Yi_L = Yi 當(dāng)使能端有效時，Yi_L = mi = Mi,Digital Logic Design and Application (數(shù)字邏輯設(shè)計及應(yīng)用),15,用譯碼器和邏輯門實現(xiàn)邏輯函數(shù),Z Y X,F = (X,Y,Z) (0,3,6,7),當(dāng)使能端有效時 Yi = mi,Digital Logic Design and Application (數(shù)字

10、邏輯設(shè)計及應(yīng)用),16,用譯碼器和邏輯門實現(xiàn)邏輯函數(shù),Z Y X,F = (X,Y,Z) (0,3,6,7),Digital Logic Design and Application (數(shù)字邏輯設(shè)計及應(yīng)用),17,= M1 M2 M4 M5,= m1 m2 m4 m5,F = (X,Y,Z) ( 1, 2, 4, 5 ),Z Y X,Digital Logic Design and Application (數(shù)字邏輯設(shè)計及應(yīng)用),18,BCD Decoder (二十進(jìn)制譯碼器),Inputs : 4-bit BCD code Outputs :1-out-of 10 Code,多余的6個狀態(tài)如

11、何處理？,輸出均無效：拒絕“翻譯”,作為任意項處理 電路內(nèi)部結(jié)構(gòu)簡單,Digital Logic Design and Application (數(shù)字邏輯設(shè)計及應(yīng)用),19,二-十進(jìn)制譯碼器,任 意 項,Digital Logic Design and Application (數(shù)字邏輯設(shè)計及應(yīng)用),20,6.4.8 Seven-Segment Decoders(七段顯示譯碼器),Normally use (常用的有)： Light-Emitting Diodes （LED,半導(dǎo)體數(shù)碼管） Liquid-Crystal Display （LCD,液晶數(shù)碼管）,Digital Logic Des

12、ign and Application (數(shù)字邏輯設(shè)計及應(yīng)用),21,21,Multiple-Output Example: BCD to 7-Segment Converter,abcdefg,f,b,d,g,e,c,(b),(a),22,Multiple-Output Example: BCD to 7-Segment Converter,a = wxyz + wxyz + wxyz + wxyz + wxyz + wxyz + wxyz + wxyz,b = wxyz + wxyz + wxyz + wxyz + wxyz + wxyz + wxyz + wxyz,a,f,b,d,g,e

13、,c,a,.,23,Input code: 4-bit BCD 輸入信號：BCD碼（用A3A2A1A0表示） Output Code: Seven-Segment Code 輸出：七段碼（的驅(qū)動信號）a g 1 表示亮(On)，0 表示滅(Off),6.4.8 Seven-Segment Decoders(七段顯示譯碼器),Digital Logic Design and Application (數(shù)字邏輯設(shè)計及應(yīng)用),24,七段顯示譯碼器的真值表,Digital Logic Design and Application (數(shù)字邏輯設(shè)計及應(yīng)用),25,Karnaugh Maps for BCD

14、-Seven-Segment Decoder (BCD - 七段顯示譯碼器的卡諾圖),Digital Logic Design and Application (數(shù)字邏輯設(shè)計及應(yīng)用),26,Karnaugh Maps for BCD-Seven-Segment Decoder (BCD - 七段顯示譯碼器的卡諾圖),Digital Logic Design and Application (數(shù)字邏輯設(shè)計及應(yīng)用),27,Karnaugh Maps for BCD-Seven-Segment Decoder (BCD - 七段顯示譯碼器的卡諾圖),Digital Logic Design and

15、Application (數(shù)字邏輯設(shè)計及應(yīng)用),28,Karnaugh Maps for BCD-Seven-Segment Decoder (BCD - 七段顯示譯碼器的卡諾圖),Digital Logic Design and Application (數(shù)字邏輯設(shè)計及應(yīng)用),29,回顧：組合電路的綜合,要求設(shè)計一個七段顯示譯碼器 邏輯抽象，得到真值表 選擇器件類型 采用基本門電路實現(xiàn)，利用卡諾圖化簡 采用二進(jìn)制譯碼器實現(xiàn)，變換為標(biāo)準(zhǔn)和形式 電路處理，得到電路圖,Digital Logic Design and Application (數(shù)字邏輯設(shè)計及應(yīng)用),30,第六章 作業(yè)（四版）,6.20 (a) (c) (e) 6.31 6.32 6.33 6.41:用MSI和SSI設(shè)計 6.43 6.38 6.47,Digital Logic Design and Application (數(shù)字邏輯設(shè)計及應(yīng)用),31,第五章 作業(yè),5.19(6.20) (a) (b) (c) 5.82(6