數(shù)據(jù)采集及顯示系統(tǒng)設(shè)計(jì)一、實(shí)驗(yàn)內(nèi)容設(shè)計(jì)一個(gè)ADC0809數(shù)據(jù)采集及顯示系統(tǒng)。采樣間隔為0.5毫秒，系統(tǒng)時(shí)鐘為512KHz。AD轉(zhuǎn)換得到的8位數(shù)據(jù)進(jìn)行譯碼顯示(顯示可采用兩位的LED)。二、系統(tǒng)框架分析與設(shè)計(jì)ADC0809是8位逐次逼近型A/D轉(zhuǎn)換器，ADC0809內(nèi)部沒有時(shí)鐘電路，故時(shí)鐘需要由外部輸入，允許范圍為10KHz?1280KHZ,典型值為640KHz,每一通道的轉(zhuǎn)換需66?73個(gè)時(shí)鐘周期。ALE是地址鎖存使能信號輸入端，在ALE信號的上升沿，ADDA?ADDC上的地址碼被鎖存、譯碼后，選通與8個(gè)模擬輸入端對應(yīng)的多路開關(guān)。START是啟動(dòng)信號輸入端，在START信號的上升沿復(fù)位A/D轉(zhuǎn)換器，下降沿啟動(dòng)A/D轉(zhuǎn)換器。根據(jù)分析，系統(tǒng)可分為采樣控制模塊、數(shù)據(jù)轉(zhuǎn)換模塊和顯示譯碼模塊三個(gè)部分，如圖1所示：三、模塊實(shí)現(xiàn)采樣時(shí)鐘產(chǎn)生模塊：由輸入、輸出時(shí)鐘的比例關(guān)系可知由256分頻器即可實(shí)現(xiàn)。具體VHDL代碼如下：LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYclkdivISPORT(RESET,CLK:INSTD_LOGIC;CLK2:OUTSTD_LOGIC);END;ARCHITECTUREONEOFclkdivISSIGNALFULL:STD_LOGIC;BEGINP_REG:PROCESS(CLK)VARIABLECNT8:STD_LOGIC_VECTOR(7DOWNTO0);BEGINIFRESET='1'THENCNT8:="00000000”;ELSIFCLK'EVENTANDCLK='1'THENIFCNT8="10000000"THENCNT8:="00000000";FULL<='1';ELSECNT8:=CNT8+1;FULL<='0';ENDIF;ENDIF;ENDPROCESSP_REG;P_DIV:PROCESS(FULL)VARIABLECNT2:STD_LOGIC;BEGINIFFULL'EVENTANDFULL='1'THENCNT2:=NOTCNT2;IFCNT2='1'THENCLK2<='1';ELSECLK2<='0';ENDIF;ENDIF;ENDPROCESSP_DIV;END;采樣控制模塊：根據(jù)時(shí)序要求來產(chǎn)生ADC0809正常工作所需的各個(gè)控制信號，采用有限狀態(tài)機(jī)設(shè)計(jì)方法實(shí)現(xiàn)采樣控制模塊，狀態(tài)由ADC0809的工作時(shí)序確定。ADC0809的工作時(shí)序如圖2所示：具體VHDL代碼如下：LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYadc_ctrlISPORT(CLK1,CLK2,RESET,EOC:INSTD_LOGIC;ALE,START,OE,ICLK:OUTSTD_LOGIC);ENDadc_ctrl;ARCHITECTUREONEOFadc_ctrlISTYPESTATESIS(S0,S1,S2,S3,S4,S5,S6,S7);SIGNALCURRENT_STATE,NEXT_STATE:STATES:=S0;BEGINPROCESS(CLK1,RESET)BEGINIF(CLK1'EVENTANDCLK1='1'ANDRESET='0')THENCURRENT_STATE<=NEXT_STATE;ENDIF;ENDPROCESS;P_STATE1:PROCESS(CURRENT_STATE,RESET,CLK2,EOC)BEGINCASECURRENT_STATEISWHENS0=>IF(RESET='0'ANDCLK2='1')THENNEXT_STATE<=S1;ELSENEXT_STATE<=S0;ENDIF;WHENS1=>IF(RESET='0')THENNEXT_STATE<=S2;ELSENEXT_STATE<=S0;ENDIF;WHENS2=>IF(RESET='0'ANDEOC='1')THENNEXT_STATE<=S3;ELSIF(RESET='0'ANDEOC='0')THENNEXT_STATE<=S4;ELSENEXT_STATE<=S0;ENDIF;WHENS3=>IF(RESET='0'ANDEOC='1')THENNEXT_STATE<=S3;ELSIF(RESET='0'ANDEOC='0')THENNEXT_STATE<=S4;ELSENEXT_STATE<=S0;ENDIF;WHENS4=>IF(RESET='0'ANDEOC='1')THENNEXT_STATE<=S5;ELSIF(RESET='0'ANDEOC='0')THENNEXT_STATE<=S4;ELSENEXT_STATE<=S0;ENDIF;WHENS5=>IF(RESET='0')THENNEXT_STATE<=S6;ELSENEXT_STATE<=S0;ENDIF;WHENS6=>IF(RESET='0'ANDCLK2='1')THENNEXT_STATE<=S7;ELSENEXT_STATE<=S0;ENDIF;WHENS7=>IF(RESET='0'ANDCLK2='1')THENNEXT_STATE<=S7;ELSENEXT_STATE<=S0;ENDIF;ENDCASE;ENDPROCESSP_STATE1;P_STATE2:PROCESS(CURRENT_STATE)BEGINCASECURRENT_STATEISWHENS0=>ALE<='0';START<='0';OE<='0';ICLK<='0';WHENS1=>ALE<='1';START<='0';OE<='0';ICLK<='0';WHENS2=>ALE<='1';START<='1';OE<='0';ICLK<='0';WHENS3=>ALE<='0';START<='0';OE<='0';ICLK<='0';WHENS4=>ALE<='0';START<='0';OE<='0';ICLK<='0';WHENS5=>ALE<='0';START<='0';OE<='1';ICLK<='0';WHENS6=>ALE<='0';START<='0';OE<='1';ICLK<='1';WHENS7=>ALE<='0';START<='0';OE<='0';ICLK<='0';ENDCASE;ENDPROCESSP_STATE2;END;數(shù)據(jù)轉(zhuǎn)換模塊：將AD轉(zhuǎn)換輸出的8位二進(jìn)制數(shù)據(jù)轉(zhuǎn)換成兩個(gè)4Bit的BCD碼。為了得到穩(wěn)定的數(shù)據(jù)將AD轉(zhuǎn)換結(jié)果進(jìn)行鎖存，具體VHDL代碼如下：LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYdat2bcdISPORT(AD_DAT:INSTD_LOGIC_VECTOR(7DOWNTO0);ICLK:INSTD_LOGIC;BCDH,BCDL:OUTSTD_LOGIC_VECTOR(3DOWNTO0));END;ARCHITECTUREONEOFdat2bcdISSIGNALTMEP_BCDH,TMEP_BCDL:STD_LOGIC_VECTOR(3DOWNTO0);BEGINP_CASE:PROCESS(AD_DAT)BEGINCASEAD_DATISWHEN"00000000"=>TMEP_BCDH<="0000";TMEP_BCDL<="0000";WHEN"00000001"=>TMEP_BCDH<="0000";TMEP_BCDL<="0000";WHEN"00000010"=>TMEP_BCDH<="0000";TMEP_BCDL<="0000";WHEN"11111101"=>TMEP_BCDH<="0101";TMEP_BCDL<="0000";WHEN"11111110"=>TMEP_BCDH<="0101";TMEP_BCDL<="0000";WHEN"11111111"=>TMEP_BCDH<="0101";TMEP_BCDL<="0001";WHENOTHERS=>TMEP_BCDH<=NULL;TMEP_BCDL<=NULL;ENDCASE;ENDPROCESSP_CASE;P_LOCK:PROCESS(ICLK)BEGINIF(ICLK'EVENTANDICLK='1')THENBCDH<=TMEP_BCDH;BCDL<=TMEP_BCDL;ENDIF;ENDPROCESSP_LOCK;END;(4)顯示譯碼模塊：將4Bit的BCD碼轉(zhuǎn)換成7段共陰LED顯示碼，具體VHDL代碼如下:LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYbcd2dispISPORT(DIN:INSTD_LOGIC_VECTOR(3DOWNTO0);LED7S:OUTSTD_LOGIC_VECTOR(6DOWNTO0));END;ARCHITECTUREONEOFbcd2dispISBEGINPROCESS(DIN)BEGINCASEDINISWHEN"0000"=>LED7S<="0111111";WHEN"0001"=>LED7S<="0000011";WHEN"0010"=>LED7S<="1101101";WHEN"0011"=>LED7S<="1100111";WHEN"0100"=>LED7S<="1010011";WHEN"0101"=>LED7S<="1110110";WHEN"0110"=>LED7S<="1111110";WHEN"0111"=>LED7S<="0100011";WHEN"1000"=>LED7S<="1111111";WHEN"1001"=>LED7S<="1110111";WHENOTHERS=>LED7S<=NULL;ENDCASE;ENDPROCESS;END;四、模塊仿真(1)采樣時(shí)鐘產(chǎn)生模塊仿真(2)采樣控制模塊仿真(3)數(shù)據(jù)轉(zhuǎn)換模塊仿真(4)顯示譯碼模塊仿真五、頂層設(shè)計(jì)及仿真頂層文件采用VHDL結(jié)構(gòu)描述法實(shí)現(xiàn)，具體代碼如下：LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;USEIEEE.STD_LOGIC_ARITH.ALL;ENTITYadc_topISPORT(CLKIN,RESIN,EOCIN:INSTD_LOGIC;AD_DATIN:INSTD_LOGIC_VECTOR(7DOWNTO0);ALEOUT,OEOUT,STARTOUT,CLK2OUT,ICLKOUT:OUTSTD_LOGIC;DISP_DATH,DISP_DATL:OUTSTD_LOGIC_VECTOR(6DOWNTO0));ENDadc_top;ARCHITECTUREONEOFadc_topISSIGNALCLK2,ICLK:STD_LOGIC;SIGNALBCDH,BCDL:STD_LOGIC_VECTOR(3DOWNTO0);COMPONENTclkdivPORT(CLK,RESET:INSTD_LOGIC;CLK2:OUTSTD_LOGIC);ENDCOMPONENT;COMPONENTadc_ctrlPORT(CLK1,CLK2,RESET,EOC:INSTD_LOGIC;ALE,START,OE,ICLK:OUTSTD_LOGIC);ENDCOMPONENT;COMPONENTdat2bcdPORT(AD_DAT:INSTD_LOGIC_VECTOR(7DOWNTO0);ICLK:INSTD_LOGIC;BCDH,BCDL:OUTSTD_LOGIC_VECTOR(3DOWNTO0));ENDCOMPONENT;COMPONENTbcd2dispPORT(DIN:INSTD_LOGIC_VECTOR(3DOWNTO0);LED7S:OUTSTD_LOGIC_VECTOR(6DOWNTO0));ENDCOMPONENT;BEGINU1:clkdivPORTMAP(CLKIN,RESIN,CLK2);U2:adc_ctrlPORTMAP(CLKIN,CLK2,RESIN,EOCIN,ALEOUT,STARTOUT,OEOUT,ICLK);U3:dat2bcdPORTMAP(AD_DATIN,ICLK,BCDH,BCDL);U4:bcd2dispPORTMAP(BCDH,DISP_DATH);U5:bcd2dispPORTMAP(BCDL,DISP_DATL);CLK2OUT<=CLK2;ICLKOUT<=ICLK;END;仿真結(jié)果如下圖:1240111111mono1010011110110101111110111111OOOOOl11101101mono010001110101ALEOUTicnaziirroeoi.itSTWOl-IT國AII_IIATIN1JHDISP_DATHB0Pointer:356.86usInterval:356.86us1列咬FiESINCUTOUTEOCIN□IHSFJiATLB0CLKIN仿真結(jié)果如下圖:1240111111mono1010011110110101111110111111OOOOOl11101101mono010001110101ALEOUTicnaziirroeoi.itSTWOl-I