實(shí)驗(yàn)三譯碼器與編碼器的設(shè)計(jì)與仿真實(shí)驗(yàn)?zāi)康模簩?shí)現(xiàn)譯碼器與編碼器的設(shè)計(jì)與仿真。二、實(shí)驗(yàn)內(nèi)容1．用邏輯圖設(shè)計(jì)3-8譯碼器，再用VHDL語言設(shè)計(jì)參數(shù)化的譯碼器；2．參照芯片74LS148的電路結(jié)構(gòu)，用邏輯圖和VHDL語言設(shè)計(jì)8-3優(yōu)先編碼器。三、實(shí)驗(yàn)步驟。（一）、8-3編碼器、3-8譯碼器的邏輯圖及邏輯表達(dá)式。1.8-3編碼器：邏輯框圖：邏輯圖：2.3-8譯碼器：2.3-8譯碼器：邏輯框圖：邏輯圖：用VHDL語言設(shè)計(jì)8-3編碼器、參數(shù)化的譯碼器。1.8-3編碼器：libraryieee;useieee.std_logic_1164.all;entitybianmaqiisport(clk,clr:instd_logic;d:instd_logic_vector(7downto0);q:outstd_logic_vector(2downto0));endbianmaqi;architectureyofbianmaqiisbeginprocess(d)begincasediswhen"01111111"=>q<="000";when"10111111"=>q<="001";when"11011111"=>q<="010";when"11101111"=>q<="011";when"11110111"=>q<="100";when"11111011"=>q<="101";when"11111101"=>q<="110";when"11111110"=>q<="111";whenothers=>q<="111";endcase;endprocess;endy;2.3-8譯碼器：libraryIEEE;useIEEE.std_logic_1164.all;entityyimaqiisport(A:instd_logic_vector(2downto0);S1,S2,S3:instd_logic;Y:outstd_logic_vector(7downto0));endentity;architectureyimaqiofyimaqiissignals:std_logic_vector(2downto0);beginS<=S1&S2&S3;process(A,S)beginY<=(others=>'1');ifS="100"thencaseAiswhen"000"=>Y<="11111110";--0when"001"=>Y<="11111101";--1when"010"=>Y<="11111011";--2when"011"=>Y<="11110111";--3when"100"=>Y<="11101111";--4when"101"=>Y<="11011111";--5when"110"=>Y<="10111111";--6when"111"=>Y<="01111111";--7whenothers=>NULL;endcase;endif;endprocess;endarchitecture;實(shí)驗(yàn)仿真結(jié)果。1.8-3編碼器：2