第三章時(shí)序邏輯的設(shè)計(jì)優(yōu)化VHDL與數(shù)字集成電路設(shè)計(jì)2storagemechanisms?positivefeedback?charge-based鎖存器：電平敏感時(shí)序邏輯電路類型寄存器：邊沿敏感DClkQClkDQDClkQClkDQ鎖存器類型基于鎖存器的設(shè)計(jì)Nlatchistransparent

whenf=0Platchistransparent

whenf=1NLatchLogicLogicPLatchf時(shí)間約束tCLKtDtc2qtholdtsutQDATASTABLEDATASTABLERegisterCLKDQ正反饋與雙穩(wěn)態(tài)Vi1ACBVo2Vi1=Vo2Vo1Vi2Vi2=Vo1雙穩(wěn)態(tài)Gainshouldbelargerthan1inthetransitionregion基本鎖存器電路DCLKCLKDConvertingintoaMUXForcingthestate(canimplementasNMOS-only)多路選擇器鎖存器Negativelatch(transparentwhenCLK=0)Positivelatch(transparentwhenCLK=1)CLK10DQ0CLK1DQ具體電路主從寄存器TwooppositelatchestriggeronedgeAlsocalledmaster-slavelatchpair具體電路Multiplexer-basedlatchpair建立時(shí)間降低時(shí)鐘負(fù)載的主從寄存器RS觸發(fā)器帶有時(shí)鐘控制的RS觸發(fā)器Cross-coupledNANDsAddedclock不同的狀態(tài)儲(chǔ)存機(jī)制DCLKCLKQDynamic(charge-based)StaticC2MOS寄存器施密特觸發(fā)器VTCwithhysteresisRestoressignalslopes

CMOS施密特觸發(fā)器MovesswitchingthresholdofthefirstinverterCMOS施密特觸發(fā)器2數(shù)據(jù)寄存器及相關(guān)電路最快數(shù)據(jù)傳遞：時(shí)鐘周期數(shù)據(jù)寄存器及相關(guān)電路最快數(shù)據(jù)傳遞時(shí)間：時(shí)鐘周期在輸入端添加控制電路，構(gòu)成其他類型的觸發(fā)器D觸發(fā)器的控制與擴(kuò)展數(shù)據(jù)寄存器及相關(guān)電路數(shù)據(jù)寄存器及相關(guān)電路D觸發(fā)器的控制與擴(kuò)展并行寄存與移位寄存數(shù)據(jù)寄存器及相關(guān)電路多功能移位寄存器數(shù)據(jù)寄存器及相關(guān)電路第四章算數(shù)邏輯單元4.1加法器4.2乘法器VHDL與數(shù)字集成電路設(shè)計(jì)加法器設(shè)計(jì)加法運(yùn)算從最低位開始，逐步向高位進(jìn)行；每一位相加時(shí)，產(chǎn)生1位結(jié)果（s），同時(shí)產(chǎn)生1位進(jìn)位（c）；最低位相加時(shí)，只需要考慮2個(gè)數(shù)據(jù)的相加：半加；其余位相加時(shí)，需要考慮3個(gè)數(shù)據(jù)的相加：全加。4.1加法器、算數(shù)邏輯單元加法器設(shè)計(jì)半加器4.1加法器、算數(shù)邏輯單元加法器設(shè)計(jì)全加器4.2加法器、算數(shù)邏輯單元利用半加單元設(shè)計(jì)全加器4.2加法器、算數(shù)邏輯單元可擴(kuò)展的串行加法器：采用全加器級(jí)聯(lián)構(gòu)成4.2加法器、算數(shù)邏輯單元4位串行加法器：ASIC設(shè)計(jì)第1級(jí)采用半加；最高級(jí)取消進(jìn)位。4.2加法器、算數(shù)邏輯單元36Full-Adder37TheBinaryAdder38ExpressSumandCarryasafunctionofP,G,DDefine3newvariablewhichONLYdependonA,BGenerate(G)=ABPropagate(P)=A?BDelete=A

BCanalsoderiveexpressionsforSandCobasedonDandP

Propagate(P)=A+BNotethatwewillbesometimesusinganalternatedefinitionfor39TheRipple-CarryAdderWorstcasedelaylinearwiththenumberofbitsGoal:Makethefastestpossiblecarrypathcircuittd=O(N)tadder=(N-1)tcarry+tsum40ComplimentaryStaticCMOSFullAdder28Transistors41InversionProperty42MinimizeCriticalPathbyReducingInvertingStagesExploitInversionProperty43ABetterStructure:TheMirrorAdder44TransmissionGateFullAdder45ManchesterCarryChain46ManchesterCarryChain47Carry-BypassAdderAlsocalled

Carry-Skip48Carry-BypassAdder(cont.)tadder=tsetup+Mtcarry+(N/M-1)tbypass+(M-1)tcarry+tsum49CarryRippleversusCarryBypass50Carry-SelectAdder51CarrySelectAdder:CriticalPath52LinearCarrySelect53SquareRootCarrySelect54LookAhead-BasicIdea

55Look-Ahead:TopologyExpandingLookaheadequations:Alltheway:56LogarithmicLook-AheadAdder57CarryLookaheadTreesCancontinuebuildingthetreehierarchically.58TreeAdders16-bitradix-2Kogge-Stonetree59Example:DominoAdderPropagateGenerate60Example:DominoAdderPropagateGenerate第四章算數(shù)邏輯單元4.1加法器4.2乘法器VHDL與數(shù)字集成電路設(shè)計(jì)8位乘法器設(shè)計(jì)：基于基本單元的擴(kuò)展設(shè)計(jì)2位乘法器：由1位乘法結(jié)果相加而成成本：4+4+4門時(shí)間：1+34.3數(shù)據(jù)累加與乘法器設(shè)計(jì)8位乘法器設(shè)計(jì)：基于基本單元的擴(kuò)展設(shè)計(jì)4位乘法器：由2位乘法結(jié)果相加而成4個(gè)2位乘法器并行運(yùn)算，產(chǎn)生4組數(shù)據(jù)，然后進(jìn)行相加。4.3數(shù)據(jù)累加與乘法器設(shè)計(jì)65TheBinaryMultiplication66TheArrayMultiplier67TheMxNArrayMultiplier

—CriticalPathCriticalPath1&268Carry-SaveMultiplier69MultiplierFloorplan70Wallace-TreeMultiplier71Wallace-TreeMultiplier72TheBinaryShifter7