MAXIICPLD:LowestPower,LowestCostCPLDFamilyEverAltera'sMAX?IIfamilyofCPLDfamilyarethelowestpower,lowestcostCPLDsever.MAXIICPLDfamilyisbasedonagroundbreakingarchitecturethatdeliversthelowestpowerandthelowestcostperI/OpinofanyCPLDfamily.WiththeintroductionoftheMAXIIZCPLD,therearenowthreevariantsthatallusethesameinnovativeCPLDarchitecture:MAXIICPLDMAXIIGCPLDMAXIIZCPLDThisinstant-on,non-volatileCPLDfamilytargetsgeneral-purpose,low-densitylogicand

portableapplications,suchascellularhandsetdesign.InadditiontodeliveringthelowestcostfortraditionalCPLDdesigns,theMAXIICPLDdrivespowerandcostimprovementstohigherdensities,enablingyoutouseaMAXIICPLDinplaceofahigherpowerorhighercostASSPorandstandard-logicCPLD.AdvancedCPLDfeaturesTheMAXIICPLDenablesahighleveloffunctionalintegrationtoreducesystemdesigncosts.ThissectiondescribestheadvancedfeaturesfoundineveryMAXIICPLD.LowpowerCPLDOne-tenththepowerconsumption(comparedto

aprevious-generation3.3-V

MAXCPLD)1.8-VcorevoltageforreducedpowerconsumptionandincreasedreliabilityCPLDindustry'sloweststandbyspecification,allowinglongeruse

inbatterypoweredapplicationsAutostart/stopcapabilityforturningofftheCPLDwhennotinuseCost-optimizedarchitectureFourtimesthedensityathalftheprice(comparedtopreviousMAX

CPLDgenerations)Designed

forminimumdiesize,givingthelowestcostperI/OpinintheindustryHighperformanceSupportforinternalclockfrequencyratesofupto300MHzTwice

theperformance(comparedtoa3.3-VMAXCPLD)UniquefeaturesOn-boardoscillator

anduser

flash

memoryReduceschipcountbyeliminatingdiscreteoscillatorsor

non-volatilestoragedevicesReal-timein-systemprogrammability(ISP)CapableofdownloadingaseconddesignwhilethedeviceisoperationalReducesthecostofremotefieldupdatesMultiVoltcoreflexibilityOn-chipvoltageregulatoraccepts3.3-V,2.5-V,or1.8-VsupplySimplifiesboarddesignwithfewerpowerrailsParallelflashloadermegafunctionImprovesconfigurationefficiencyofnon-JTAG-compliantflashdevicesontheboardSimplifiesboardmanagementbyallowingJTAGcommandimplementationviatheMAXII

CPLDI/OcapabilitiesMultiVoltI/Ocapabilityallowsinterfacewithdevicesat1.5-V,1.8-V,2.5-V,or3.3-VlogiclevelsSchmitttriggers,programmableslewrate,and

programmabledrivestrengthimprovesignalintegrityEasiest-to-usesoftwareAltera’sno-costQuartus?

IIWebEditionsoftwaresupportsalldevicesintheMAXIICPLDfamily

and

optimizespin-lockedfitting

andperformanceNewMAX+PLUS?

IIlook-and-feeloptionintheQuartusIIsoftwareenhanceseaseofuseCPLDApplicationsTheMAXIICPLDfamilytargetscommoncontrolpathapplications,including:Power-upsequencingSystemconfigurationI/OexpansionInterfacebridging

MAXIICPLD系列概述及應用

Altera的MAX?II系列CPLD是有史以來功耗最低、成本最低的CPLD。MAXIICPLD基于突破性的體系結(jié)構(gòu)，在所有CPLD系列中，其單位I/O引腳的功耗和成本都是最低的。隨著MAXIIZ的推出，有三種型號產(chǎn)品都使用了同樣的創(chuàng)新CPLD體系結(jié)構(gòu)：MAXIICPLDMAXIIGCPLDMAXIIZCPLD這一瞬時接通的非易失器件系列面向蜂窩手機設計等通用低密度邏輯應用。不但具有傳統(tǒng)CPLD設計的低成本特性，MAXIICPLD還進一步提高了高密度產(chǎn)品的功耗和成本優(yōu)勢，這樣，您可以使用MAXIICPLD來替代高功耗和高成本ASSP以及標準邏輯CPLD。

MAXII器件系列的高級特性MAXIICPLD支持高級功能集成，以降低系統(tǒng)設計成本。這一部分介紹MAXIICPLD的高級特性。低功耗

十分之一的功耗(和前一代3.3VMAX器件相比)1.8V內(nèi)核電壓降低了功耗，提高可靠性。CPLD業(yè)界最低的待機規(guī)范，大大延長了電池供電時間。自動啟動/停止功能，CPLD不使用時關(guān)斷。低成本體系結(jié)構(gòu)

以一半的價格實現(xiàn)四倍的密度(和前一代MAX器件相比)通過設計，減小了管芯面積，單位I/O引腳成本在業(yè)界是最低的。高性能

支持高達300MHz的內(nèi)部時鐘頻率性能加倍(和3.3-VMAX器件相比)獨特的特性

板上振蕩器和用戶閃存不需要分立振蕩器或者非易失存儲器，減少了芯片數(shù)量。實時在系統(tǒng)可編程能力(ISP)器件工作時，可下載第二個設計。降低了遠程現(xiàn)場更新的成本靈活的MultiVolt內(nèi)核片內(nèi)電壓穩(wěn)壓器支持3.3-V、2.5-V和1.8-V供電減少了電源數(shù)量，簡化了電路板設計。并行閃存加載程序宏功能

提高了板上不兼容JTAG閃存的配置效率通過MAXII器件實現(xiàn)JTAG命令，簡化了電路板管理。I/O能力

MultiVoltI/O支持和1.5-V、1.8-V、2.5-V以及3.3-V邏輯電平器件的接口施密特觸發(fā)器、可編程擺率和可編程驅(qū)