XC3S500E-PQG208XilinxSpartan3EPL2303USBTO2X64MbitIndependentLDOO3.3VLDOO2.5VLDOO1.2VM25P1616MbitsSPIAD7478SPISerial8bitsADCwithAD5300SPISerial8bitsDACwithOP340OpENC28J60T/SS10MHR911105ANetwork50MHZ12MHZ25MHZUSBDC2.0PowerPushPowerSwitchselectPowerADCinputandDACUserJTAGProgram4bitsS144BitsSevenSegmentIN4148LEDsystemstate4bitsSevenSegmenty4bits4bitsSevenSegmenty4bitsADCUser源。500MA的絲，起到過流保護作用。LDOASM117-3.3V3.3V電壓.LDOASM117-2.5V2.5V電壓.LDOASM117-1.1V提供1.2V電壓.50MHZ16Mbits的SPIFLASH,還有配置模式M0,M1,M2的配置。FPGA0.1ufP3口XC3S500E-PQG208ADCAndAD74781MSPS8bitsSPIADC.AD53001MSPS8bitsSPIDAC.OP340運放.2片獨立的USB轉VGA4LEDS410MIO75,IO94,IO87,IO69VAG,PS24LEDIO129,IO13224LC02GPIORunLed1難度等級Figure1:RunLedTable1:ModuleFunctionSystemSystemDrive4bits3 4 5output[3:0]Led;7reg[3:0]8reg[1:0]9reg[24:0]10wire12assignC1_Clk=(C1== )?1:14always@(posedgeClk if(!Rst)C1<= elseif(C1< )C1<=C1+1'b1;//C1Timecounter elseC1<=19always@(posedgeClk elseif(C1_Clk) Ledn<=Ledn+ always@(posedgeClkelse 2830TopModuleSubModulemainmodule,Module。TopmoduleFPGA的管腳了。這個會在我們把這個代碼講完后，在是開發(fā)板上從FPGA管腳連線到物理元件的信號。()input，指示信號是輸入到模塊的信號，比如 這種中括號[a:b]C，的寫法稍微有點不同，并且表示的意義要簡單一些，主要是為了簡化表示的方式。Outputwire,output,inout類型。Inout表示輸入輸出類型。這種類型，我們的例子中在24LC02中有使用。reg，指示寄存器，比如reg[3:0]Led;表示了一組寄存器注意，我們一般常用的信號類型有input,output,inout,wire.always@()always@(posedgeClk)敏感信號posedgeClk含義是在上升沿的時候有效，敏感信號還可以negedgeClk含義是下降沿的時候有效，還可以是*這個一符號。如果是一個*則表示一直是敏感的。assign用來給output,inoutwire這些類型進行連線，注意，這里用連線，而不是賦值，assign是表示的線型信號，是物理線路。if()else()，判斷，和高級語言一樣的用法if()elseif()，判斷，和高級語言一樣的用法always@(posedgeclkbegin非阻塞賦值A<=B;C<=always@(posedgeclkbegin阻塞賦值A=B;C=+，-，*，，%veriolg中還可以使用這些，這些使用C語言基本是一樣的，不同之處主要是這些都要占用硬件資源是不能無限使用的。此外，對于/,和%2的冪，這點有的時候比較頭痛。A<BA和BABTURE,FALSE,看以上L14-L17之間的代碼，小于號被用在了條件判讀語句中。<=A<=BABABTURE,否則為>A>BABABTURE,否則為FALSE>=小于等于，比如A>=B含義就是AB比較，如果大于等于BTURE,否則為A>>2A2A<<2A2~A=8’b1111_0000;~A&A=8’b1111_0000;B=8’b1010_1111;A&B;&&邏輯與，比如A=1,B=2;A&&BTRUE;A=1,B=0,A&&BA=B?C:D是一個條件運算符，含義是如果B為TRUE則把C連線A,否則把D連線A.比如我們這段代碼中assignC1_Clk=(C1==25'd )?1:0;C1_Clk,是一個wire類型的信號，當C1==25'd 時候，連線到1，否則連線到0.｛｝,verilog中，大括號是起到銜接的作用,比如，我看可以把｛FALSH0，TRUE50%的語法內容了。但是除Figure2:Pathanddelay,語句，if()elseif()嵌套語句。1moduleRunLed_tb;3//Inputs4regClk;5regRst; //7wire[3:0]8//InstantiatetheUnitUnderTest(UUT)9RunLeduut(10 initial Clk=

Rst=#10Clk=#10Clk=#10Clk=forever#10Clk=25到FPGA中運行的，仿真代碼則不需要，因此，仿真代碼更具有靈活性。TopModuleRunLedSubModuleRunLed添加的forever#10ClkClk;20nsforever故名Figure RunLed2難度等級3 4 5output[3:0]Led;reg[3:0]reg[24:0]11assignC1_Clk=(C1== )?1:13always@(posedgeClk if(!Rst)C1<= elseif(C1< )C1<=C1+ elseC1<=18always@(posedgeClk if(!Rst)elseif(C1_Clk)Led<={Led[2:0],23這段代碼中，采用了移位方式，來控制LED的點亮。比如：Led<={Led[2:0],Led[3]};用是把Led[2:0]三位移到，把Led[3]移到低位，以此來實現(xiàn)移位。Button難度等級Figure1:ButtonTable1:ModuleFunctionDrive4bitsInputInputFigure2:Buttonmoduleinputinputinputinputoutput[3:0] 8reg[20:9reg[20:reg :0reg :0reg 15assignSw1Up=Sw1D&&!Sw1D1;17assignSw2Up=Sw1D&&!Sw2D1; if(!Rst)begin19always@(posedgeif(!Rst)begin1'b0;Sw2D1<=else <=Sw1D;Sw2D1<= if(!Rst Sw1D<=1'b1;Sw2D<=elseif(C1[20])Sw1D<=40always@(posedge elseif(!Sw1D&&40always@(posedge if(C2[20])Sw2D<=elseif(!Sw2D&&C2==0)Sw2D<=1'b1; if(!Rst C1<=21'd0;C2<=elseif(!Sw1)beginif(!C1[20])C1<=C1+1'b1;elseif(C1>0)C1<=C1- if(!Sw2)beginif(!C2[20])C2<=C2+1'b1; elseif(C2>0)C2<=C2- 52always@(posedge4'd0;Led<=)Ledn<=Ledn+elseif(Sw2Up)Ledn<=Ledn-Led<=Led[Ledn]<= 63UartLoop難度等級Figure1:UartLoopTable1:mainModuleFunctionSystemUartserialUartserialTopmoduleSubmoduleModulemainmodule wire9 U1 TopmoduleUartRxdUartRxd和UartTxd都是子模塊的名字，U1,U2是給子模塊在主模塊中取的名比如U1中.IsDone(IsRxdDone),的含義是IsDoneUartRxd的信號，而IsRxdDoneUartRxdIsDone需要的信號。也就是說括號內Figure3:UartTxdTable3:UartTxdModuleFunctionSystemUartserialStartSendDatawhenfrom0toDatahavebeensentwhenfrom0toDataneededtobeenIsSat011Figure4:Uart接著我們看下Uart1moduleUartTxd(Clk,IsSta,Din,IsDone,Txd);inputinputinput[7:0]output9reg[10:0]regregalways@ Clk //boundrate Clk: Clkdivider:if(ClkEn) if(C1<11'd1301)beginClkt<=11'd0;C1<=C1+1'b1;elsebeginClkt<=1'b1;C1<=11'd0;elsebeginClkt<=1'b0;C1<=11'd0;end20reg21always@ Clk) 2325parameterIDLE=26parameterSEND=1'b1;28regregregreg[7:0]DBin[3:0]reg[9:0]reg[2:0]wirereg37assignTxdUp=IsSta1&(!IsSta2);39always@(posedgeClk) if(TxdUp)begin//4bitsDBin[1]<=DBin[0];DBin[2]DBin[1]<=DBin[0];DBin[2]<=DBin[1];DBin[3]<= C2<=C2+ if(C2<3'd2)IsDone<=1'b1;elseIsDone<=1'b0; i<=1'b0;Txd<=1'b1;ClkEn<=1'b0;Dsin[0]<=1'b0;Dsin[9]<= if(C2>0&&(!TxdUp))beginDsin[8:1]<=DBin[C2-1'b1];C2<=C2-1'b1;s<=SEND;ClkEn<=1'b1;end if(Clkt)beginif(if(Clkt)beginif(i<)beginTxd<=Dsin[i];i<=i+1'b1;endelses<= 6162FLASH即發(fā)送緩沖區(qū)空閑，則發(fā)送模塊發(fā)送緩沖區(qū)1byte的數(shù)據(jù)，并且進入SEND狀SEND10bits1bit起始位，8bits數(shù)據(jù)為，1bit()Figure5:case我們這里的通信波特率是38400，而我們的系統(tǒng)時鐘是50MHZ因此分頻系數(shù)為方式，define的方式，隨著我們的深入講解也會遇到的。parameterIDLE1'b0;parameter常量的用法。Parameterchipscope中是可以被查看的這一點很重要，有別于define.assignTxdUp=IsSta1&always@(posedge Clk)begin穩(wěn)態(tài)。如果需要更穩(wěn)定，可以多寄存幾次。此外通過TxdUp提取信號的上升沿。Figure6:Threeregisters會另自我修護能力較弱的系統(tǒng)直接。接下來我們分析這種串擾的概率問題。Figure7所示為一個正常第一級寄存器發(fā)生了亞穩(wěn)態(tài)，第二級、第三極寄存器Figure7:Metastable寄存器能到一個穩(wěn)定的值。但是為什么第二級寄存器還是可能會產生亞穩(wěn)態(tài)呢？8:ModuleUart3 4output[7:0]5output6input 8reg9reg[6:10reg12always@(posedge Clk)//Clk:50MHZ Clkdivider:80 16timessampleratesofboundrate if(Clk16En if(C1<7'd80)beginClk16<=7'd0;C1<=C1+elsebeginClk16<=1'b1;C1<=7'd0;endelsebeginClk16<=1'b0;C1<=7'd0;end regalways@( Clk)RxdD1<=Rxd;RxdD2<=regreg[7:0]reg[3:0]reg[3:0]reg[3:0]regIsSta=reg[0:0]s=always@(posedgeClk)IsDone<=case(s

i<=4'd0;C2<=4'd0;C3<=4'd0;IsSta<=1'b0;Clk16En<=if(RxdD2&&(!RxdD1))beginClk16En<=1'b1;s<=SAMP;if(C2<4'd15) C2<=C2+ if(!RxdD2)C3<=C3+1;elseC3<=

else C2<=4'd0;C3<= if(!IsSta i<=4'd0;if(C3>4'd7)IsSta<=1'b1;elsebeginIsSta<=1'b0;s<=elseif(i<4'd8 if(C3>4'd7)Dout[i]<=1'b0;elseDout[i]<=1'b1;i<=i+ IDLESAMP兩個狀IDLERXDSAMP狀態(tài)采樣起始TURE8bit數(shù)據(jù)。8bit12次，并且 以上為UartLoopISEchipscope中對本設計的信號進行的采樣UartBlockRam難度等級BlockRAMUartFPGA，被FPGA接收并且到FPGA的BlockRam,之后數(shù)據(jù)被從內存中被讀出發(fā)送到PC的軟TheBlockMemoryGeneratorcoreusesembeddedblockRAMtogeneratefivetypesofSimpleDual-portDual-portSinglePortFigure選擇SinglePortFigure2:Single-port簡單單端口RAM2 SimpleDual-port簡單雙端口有AB3A可以寫，端口BFigure4:TrueDual-port真雙端口有A和B4FigureFigure6:WriteFirstModeFigure7:ReadFirstModeFigure8:NoChangeMode無變化模式：如果WEA為高數(shù)據(jù)寫入內容，但是輸出的數(shù)據(jù)不變化，知道WEA為低，輸出數(shù)據(jù)有地址決定。我們設置寬度為8bits256bytes,模式為先寫模式5所示。FigureFigure11:Spartan3BlockMemory:RegisterPort[A|B]OutputsofMemoryPrimitivesandMemoryCoreOptionsBockRam向導，允許設置可以寄存器輸出，這種方式可以提高性能。用戶可以在兩個地方包含寄存器級，BlockRam基10..

FigureFigureModulemodule wirewire wire[7: [7:wire[7: [7: [7:always@(posedgeClkif(!Rst Wea<=1'b0;Addra<=8'd255;Dina<=8'd0;Din<=endelseif(IsRxdDone <= <= <=if(IsTxdDone)IsSta<=UartRxdU1 assignRsta=BRAM.wea(Wea),//Bus[0:.addra(Addra),//Bus[7:.dina(Dina),//Bus[7:.douta(Douta));//Bus[7:44BlockRamBlockRamBlockRAM閑時間取出數(shù)據(jù)，給Uart的發(fā)送模塊進行發(fā)送。來講解。UartLoop中已經對Uart做了比較詳細的說明故相同的代碼不再重復說明。PS2Uart難度等級Figure1:PS2UartTable1:mainModuleFunctionSystemSystemUartserialPS2PS2SerialFigure2:UartFigure2PSClk8PSClkUartUart(makecode)和斷碼(breakcode)。當一個鍵被按下或持續(xù)按住時,鍵盤會將該鍵的通碼發(fā) “W”鍵的時候，依然會輸出“8'hf08'h1d”鍵的“斷碼”。每次我們按下鍵盤，到接收到斷碼后，IsDownTRUEUart發(fā)送模塊發(fā)送到PC上。Figure2keyboardcodeModuleinputinputinputinputwirewire 13UartTxdu2(.Clk(Clk),.IsSta(IsDown),.Din(RdData),.Txd(Txd));15Module3input4input 77output[7:0]inputinputoutputIsDown; 10 12regIsDown;//Keyis13reg14reg[7:0] 15reg[7:0]16reg[7:0]17reg[3:0]19wirePSCLKNp;21always@(posedgeClkornegedge if(!Rst) PSClk0<=1'b0;PSClk1<= else PSClk0<= PSClk1<= 30assignPSCLKNp=~PSClk0&PSClk1; //negedge 32 34always@(posedgeClkornegedgeRst) if(!Rst) C1<=RdDataR1<=case4'd0:if(!PSData)C1<=C1+1'b1;//ifPSDataislowdetected C1<=C1+RdDataR1[C1-1]<= 4'd9: C1<=C1+ 4'd10:// C1<=default: always@(posedgeClkornegedgeif(!Rst)IsDown<=RdDataR2<= if(RdDataR1==8'hf0)IsDown<=1'b1;//8'hf0keyfromdowntoelsebegin//keyIsDown<=RdDataR2<=70always@(posedgeClk) case 8'h15:PSASCII<= 8'h1d:PSASCII<= 8'h24:PSASCII<=8'h2d:PSASCII<=8'h2c:PSASCII<=8'h35:PSASCII<=8'h3c:PSASCII<=8'h43:PSASCII<=8'h44:PSASCII<=8'h4d:PSASCII<=8'h1c:PSASCII<=8'h1b:PSASCII<=8'h23:PSASCII<=8'h2b:PSASCII<=8'h34:PSASCII<=8'h33:PSASCII<=8'h3b:PSASCII<=8'h42:PSASCII<=8'h4b:PSASCII<=8'h1a:PSASCII<=8'h22:PSASCII<=8'h21:PSASCII<=8'h2a:PSASCII<=8'h32:PSASCII<=8'h31:PSASCII<=8'h3a:PSASCII<= default: 100102assignRdData=PSASCII;104VGA難度等級Figure1:VGATable1:VGAModuleFunctionSystemButtonFigure2:hsyncFigure3:vsync800X600abcde(total800X600X72opqr的速度只要大于125次，我們人眼看上去圖像就是連續(xù)的。所以Fre= /692640=72HZ,完全滿足了大于1秒25次的要求。elseHS<=1;代碼是產生水平場同步信號，if(638<= T<=644)VS<=0;elseVS<=1;是產生豎直場同步信號。顯示器的顯示是從左上角開始，從左到右從上到下域，在L36-410-199，200-399，400-599.L44-L54,就是通過外部按鈕Figure6顯示。10，01顯示是這個兩個的組合，大家可以做實驗獲取結果。FigureFigureFigure1module 2 3 [1:0] output output 7outputHS,VS; 9reg 10reg T;//HS 11reg[911reg[9 T;//VS13reg 14reg 15reg 16reg 17reg 19always@(posedgeClk)begin//HSVS if(857 T<=977)HS<=0;elseHS<=T<=T== T<=T==T<=T<=0;TT+ T T+ if(638 T<=644)VS<=0;elseVS<=27 29always@(posedgeClk) //Hshow 0 T<=266)&&(0 Telseif((267<= T<=599)){RED_H,GREEN_H,BLUE_H}<=3'b100;elseif((534<= T<=599)){RED_H,GREEN_H,BLUE_H}<=3'b010;534)&&(0 T799)&&(0 T elseif((0 T elseif((0 T<=799)&&(200 T if((0 T<=799 0 T elseif((0 T<=799)&&(400 T always@(SWorRED_HorGREEN_HorBLUE_HorRED_VorGREEN_VorBLUE_V)//vagoutput =;= 54SHIFT8難度等級Figure1:SHIFT8Table1:ModuleFunctionShiftClock:DatashiftformlowtohighateachraisingLoaddatatoshiftregisterwhenWhenIsLoadhighdatawillbeloadedintoshiftBitdatashiftedintoshiftregisterateachraisingedgeofBitdatashiftedoutfromshiftregisterateachraisingedgeofFigure2:SHIFT8ModuleIsLoadTRUEDataIn被模塊寄存器DataIntIsLoad1module inputinputinputinputinput[7:0]inputinputoutputoutputreg[7:0]DataInt;assignalways@(posedgeClk if(!Rst)DataInt<= elseif(IsLoad)DataInt<= elseif(SlClk)beginif(SftEn)DataInt<={DataInt[6:0],SftIn}; 241moduleSHIFT8_tb;//regregregregreg[7:0]regreg//wirewire[7:0]//InstantiatetheUnitUnderTestSHIFT8uut initialIsLoad=DataIn=IsLoad=DataIn=SlClk31 Rst= SftIn= SftEn=#10#10Clk=!Clk;#10Clk=!Clk;#10Clk= Rst=forever#10Clk= 46 reg[3:0]47 always@(posedgeClk)SlClk<=!SlClk;if(!Rst)beginIsLoad always@(posedgeif(!Rst)beginIsLoad51 1'b1;DataIn<=8'hAA;SftIn<=1'b0;C1<=elseif(SlClk)if(C1<4'd8)beginIsLoad<=1'b0; SftEn<=1'b1;SftIn<=!SftIn;C1<=C1+1'b1;endelsebeginSftEn<=1'b0;C1<=4'd0;DataIn<=8'h00;IsLoad<=1'b1; 59ExpandIO難度等級Figure1:mainTable1:mainModuleFunctionSystemSystem74hc595Lach74hc595Serial74hc595Shift74hc595Table2:ExIO16ModuleFunctionSystemSystem74hc595Lach74hc595Serial74hc595Shift74hc595Table3:spiModuleFunctionSystemSystemMasterOutSerialMasterInSerialSpi1:StartSpi1bytehavebeen WriteDataRegisterReadDataRegister2:Figure3:SpiTable4:ShiftModuleFunctionSystemSystemShiftClock:DatashiftformlowtohighaleachraisingLoaddatatoshiftregisterwhenWhenIsLoadhighdatawhilebeloadedintoshiftregisterBitdatashiftedintoshiftregisterateachraisingedgeofBitdatashiftedoutfromshiftregisterateachraisingedgeofFigure4:SpiState存器來完成。傳送結束后，使能IsDone信號，通知上層模塊傳送結束。如果不為TRUE,則回到狀態(tài)0.Module outputoutput output[7:0] [7:0] output14 [1:0]15 16 18 20 21 22 25wire26wire28 29wire31assign32assign33always@(posedgeClk)SckD1<=Sck; 35parameterBIT8=37always@(posedgeClk)//countshifted38if(SckEn&&SckUp)BitC<=BitC+1'b1;elseif(BitC==BIT8)BitC<=4'd0; 40assignMosi=DirSet?SftOut:1'b1;42always@(posedgeClk)//main43 s<=1'b0;IsDone<=1'b0;SckEn<=else0://IDLEbeginIsDone<=1'b0;IsDone<=1'b0;SckEn<=1'b0;if(IsSta)s<=1'b1;1://shift SckEn<=1'b1;if(BitC==BIT8)beginRdData<=DataOut;SckEn<=1'b0;IsDone<=1'b1;s<=1'b0;end57//spiclockgenerator59parameterTSET=7'd1;always@(posedgeClk)//ShiftClockif(!Rst)beginSckC<=7'd0;Sck<=1'b0;SckState<=elsecase(SckStatebeginSckC<=7'd0;Sck<=1'd0;if(SckEn)SckState<=2;Sck<=1'b1;if(SckC>=TSET)beginSckState<=2;SckC<=7'd0;endelse<=SckC+0;0;if(SckC>=TSET) SckC<=7'd0;if(SckEn)SckState<=1;elseSckState elseSckC<=SckC+ 787880wire81 82 SlClk=DirSet?SckNp:83assignIsSpiLd=84SHIFT8 970狀態(tài)，設置方向為輸出方向，IsStaFALSE,8bitsFigure5:SpiTransmitModulemodule outputoutputoutputoutput 11reg12reg14reg15reg16reg17reg19wire21always@(posedge DirSet<=1'b0;IsSta<=1'b0;s<=1'b0;LchClk<=1'b0;SRst<=else0beginDirSet<=1;IsSta<=0;s<=3'd1;SRst<=1; 1,2://nop2s<=s+ //WriteMSBBYTEOfbeginWrData<=ExIO[15:8];IsSta<=1;SRst<=1;s<=4; beginIsSta<=0;if(IsDone)begins<=5;LchClk<=0;end 5 //WriteLSBBYTEOfbeginWrData<=ExIO[7:0];IsSta<=1;s<=6; beginIsSta<=0;if(IsDone)begins<=0;LchClk<=1;endspi56Modulemodule 9reg[15:0]10reg[22:0]always@(posedgeif(!Rst)beginC1<=23'd0;elseif(C1<)C1<=C1+ ExIO[15]<=C1<=30SpiDisy難度等級12個，動態(tài)驅動4位7段數(shù)碼管顯示0，1，2，3。Table1:mainModuleFunction

Figure1:mainSystemSystem74hc595Latch74hc595Serial74hc595Shift74hc595Table2:Dpy4ModuleFunctionSystemSystem74hc595Lach74hc595Serial74hc595Shift74hc59574hc595OutputLed074hc595OutputLed174hc595OutputLed274hc595OutputLed3Table3:spiModuleFunctionSystemSystemMasterOutSerialMasterInSerialSpi1:StartSpi1bytehavebeen WriteDataRegisterReadDataRegisterTable4:Codemapto08192A3B4C5D6E7F和上面的ExpandIO一樣的，不再累述。moduleinputinputoutputoutputoutputoutput 13 zero=8'b1100 =8'b1111three=8'b10110000,four=three=8'b10110000,four=8'b1001eight=8'b10000000,nine=eight=8'b10000000,nine=seven=8'b1111 =8'b1000 IDLEBYT0BYT1regregregregregregregregregregreg45wirealways@(posedge DirSet<=1'b0;IsSta<=1'b0;s<=1'b0;LchClk<=1'b0;SRst<=else0beginDirSet<=1;IsSta<=0;s<=3'd1;rdy<=0;SRst<=1; 1,2://nop2s<=s+ //WriteMSBBYTEOfbeginWrData<=dp;IsSta<=1;SRst<=1;s<=4; beginIsSta<=0;if(IsDone)begins<=5;LchClk<=0;end 5 //WriteLSBBYTEOfbeginWrData<=dat;IsSta<=1;s<=6; beginIsSta<=0;if(IsDone)begins<=0;LchClk<=1;rdy<=1;endif(rdy)beginDpy_n<=Dpy_n+if(Dpy_n>3)Dpy_n<=1'b0; always@(posedgeClkcase(Dpy_nbegindata<=Dpy0;dp<=begindata<=Dpy1;dp<=85

begindata<=Dpy2;dp<=begindata<=Dpy3;dp<=4'b0001;endalways@(posedgeClkcase(data1:dat<=one;2:1:dat<=one;2:dat<=3:dat<=4:dat<=5:dat<=6:dat<=7:dat<=8:dat<=9:dat<=spiModulemodule 9wire[3:0]Led1=10wire[3:0]Led2=11wire[3:0]Led3=wire[3:0]Led4=Dpy427SpiCounter雖然通過前面兩個設計，我們可以熟練運用PI這個模塊了，但是在g中如果能夠實，我們74c595擴展6個IO并且使用其中12個動態(tài)驅動4位7段數(shù)碼管顯示—999。Figure1:ExpandIOTable1:mainModuleFunctionSystemSystem74hc595Latch74hc595Serial74hc595Shift74hc595Table2:Dpy4ModuleFunctionSystemSystem74hc595Lach74hc595Serial74hc595Shift74hc59574hc595OutputLed74hc595OutputLed74hc595OutputLedTable3:spiModuleFunctionSystemSystemMasterOutSerialMasterInSerialSpi1:StartSpi1bytehavebeen WriteDataReadDataModulemodule 9reg[3:0]10reg[3:0]11reg[3:0]12reg[3:0]Led1;14reg[6:0]15reg[9:0]16reg[13:0]19reg[22:0]20reg[3:0]i,j,23always@(posedgeClk if(!Rst) i<=4'd0;j<=4'd0;k<=4'd0; else if(C4> if(1000*(k+1)<=C4)k<=k+1'b1;elsebeginLed4<=k;C3<=(C4-1000*k);k<=4'd0;end endelsebeginC3<=C4;Led4<=4'd0;end if(C3> 100*(i+1)<=C3)i<=i+1'b1;elsebeginLed3<=i;C2<=(C3-100*i);<=4'd0; endelsebeginC2<=C3;Led3<=4'd0;end if(C2> 10*(j+1)<=C2)j<=j+1'b1;elsebeginLed2<=j;Led1<=(C2-10*j);endelsebeginLed1<=C2;Led2<=4'd0;always@(posedgeif(!Rst) C5<=23'd0;C4<=C5<=C5<= if(C5<))C5<=C5+if(C4<14'd9999)C4<=C4+1'b1;elseC4<= Dpy465是4。ADCAD7478難度等級Figure1:ADCAD7478Table1:T24LC02ModuleFunctionSystemSystem74hc595Latch74hc595Serial74hc595Shift74hc595AD7478ChipSerialDataoutputtoAD7478FastThroughputRate:1MSPSSpecifiedforVDDof2.35Vto5.25VLowPower:3.6mWTypat1MSPSwith3V15mWTypat1MSPSwith5VsWideInputBandwidth:70dBSNRat100kHzInputFrequencyFlexiblePower/SerialClockSpeedManagementNoPipelineDelaysHigh-SpeedSerialInterfaceStandbyMode:1 AMax6-LeadSOT-23PackageBattery-PoweredalDigitalAssistantsMedicalInstrumentsCommunicationsInstrumentationandControlSystemsDataAcquisitionSystemsHigh-SpeedFigure2:AD7478PinFigure3:AD7478InterfaceFigure4:AD7478 1module inputinputinputoutput outputregoutputreg reg[11:012reg13reg14reg[315reg[319reg20wire22assignClkNp=23assignClkUp=(SClk)&&(!SClk1);25reg26always@(posedgeClk)if(s!=0)SClk<=!SClk;elseSClk<=1'b1;28always@(posedgeClk //IsSta1<= SClk1<=3133always@(posedgeClk if(!Rst s<=4'd0;IsBusy<=1'b0;C<=4'd0;AIReg1<=12'd0;Sync<=endelsecase Sync<=1'b1;IsBusy<=1'b0;C<=if(IsSta IsBusy<=1'b1;s<=4'd1;Sync<=1'b0;if(ClkUp) s<=s+1'd1;if(C<4'd12if(ClkUp)beginSync<=1'b0;AIReg1[11:0]<={AIReg1[10:0],AI};C<=C1'b1; if(ClkUp)beginC<=4'd0;s<=4'd6;Sync<=1'b1;AIReg<=AIReg1;if(ClkUp)s<=56module 13reg[3:0]14reg[3:0]15reg[3:0]16reg[3:0]Led1;18reg[6:0]19reg[9:0]20reg[13:0]23reg[22:0]24reg[3:0]i,j,26reg27wirealways@(posedgeClkIsSta<=if(!IsBusy)C4<= if(!Rst) i<=4'd0;j<=4'd0;k<=4'd0; else if(C4> if(1000*(k+1)<=C4)k<=k+1'b1;elsebeginLed4<=k;C3<=(C4-1000*k);k<=4'd0;end endelsebeginC3<=C4;Led4<=4'd0;end if(C3> 100*(i+1)<=C3)i<=i+1'b1;elsebeginLed3<=i;C2<=(C3-100*i);<=4'd0; endelsebeginC2<=C3;Led3<=4'd0;end1010*(j+1)<=C2)j<=j+1'b1;elsebeginLed2<=j;Led1<=(C2-10*j);if(C2><=4'd0;end endelsebeginLed1<=C2;Led2<=4'd0; 47 6060DACAD5300難度等級Figure1:DACAD5300Table1:mainModuleFunctionSystemSystemAD5300ChipSerialDataoutputfromSingle8-BitMicropowerOperation:140A@5VPower-Downto200nA@5V,50nA@3V2.7Vto5.5VPowerSupplyGuaranteedMonotonicbyDesignPower-OnResetto0VLowPowerSerialInterfacewith itt-TriggeredInputsRail-to-RailOperationPortableBattery-PoweredInstrumentsDigitalGainandOffsetAdjustment Figure2:AD5300PinFigure3:AD5300InterfaceFigure3:AD5300InputRegisterFigure5:AD53001module inputinputinputoutputoutputregoutputregoutputreg [15:0regregreg[4regwire20assignClkNp=21assignClkUp=(SClk)&&(!SClk1);23always@(posedgeClk)SClk<=!SClk;25always@(posedgeClk SClk1<=2729always@(posedgeClk if(!Rst s<=2'D0;IsBusy<=1'b0;C<=5'd0;AOReg1<=16'd0;Sync<=endelsecase Sync<=1'b1;IsBusy<= C<=if(IsSta)beginAOReg1<=AOReg;IsBusy<=1'b1;s<=1'b1;if(ClkNp)beginSync<=1'b0;s<=2'd2;if(C<5'd16if(ClkUp)beginSync<=1'b0;AO<=AOReg1[15];AOReg1[15:0]{AOReg1[14:0],1'b0};C<=C+1'b1;elseif(ClkNp)beginC<=5'd0;Sync<=1'b1;s<=2'd3;elseif( s<= 5052module outputoutputregassignalways@(posedge14reg[15:0]15reg16wire17regs=19always@(posedge IsSta<=0:if(AOReg[11:4]<8'd255)AOReg[11:4]<=AOReg[11:4]+1'd1;elses1:if(AOReg[11:4]> )AOReg[11:4]<=AOReg[11:4]-1'd1;elseselseIsSta<=42I2C24C02難度等級24LC021BYTE數(shù)據(jù)，然后，讀出這個地址的數(shù)據(jù)，并Figure1:I2C24C02Table1:T24LC02ModuleFunctionSystemSystem74hc595Latch74hc595Serial74hc595Shift74hc595I2CI2CdataTable2:I2CModuleFunction

Figure2:I2CI2CserialI2CserialReadWrite1:StartSenddata0:StopSend1:WriteAck processhavebeen processisResetFigure3:24LC02Table3:UartTxdModuleFunctionSerialdataSerialclockdataWriteFigure4:I2cFigure5:I2cACKACK

Figure5:24LC02Byte

Figure6:24LC02Randomread調用I2CIPCOREWriteReadWriteHeaderFigure7:24LC02WriteRead8bits頭部數(shù)據(jù)，如果在此階段檢測到產生停止位命令，則進入STOP，產生停止位，IDLE,8bitsACK_HEADERACK_HEADER：SCL為高電平，并且滿足高電平持續(xù)時間后，檢測從機ACKSDA0ACKACK。ACKXMIT_DATA，如果是接收則進入RCV_DATA；ACK錯誤：則進入STOP，產生停止位。8bitsSTO，產生停止位，IDLE,8bitsACK_XMIT。則回到XMIT_DATAACK錯誤：則進入STOP，產生停止位。WAIT_ACKACK_DATA階段IDLE狀態(tài)，如果有停止位產生請求，則進入STOP,RCV_DATA間，產生停止位，之后回到IDLETModulemoduleI2C output outputoutputoutputoutput SclC1_HIGH= = = =27 CLR_REG= 28 T=29 =30parameter =4'b0000; 32parameter =34parameterMScl_IDLE=35parameterMScl_HIGH=36parameter = = = = = = = =50reg52reg53reg55reg56reg58reg59reg61reg63reg64reg65reg66reg68wire69wire70wireregwirewirewire[7:0] reg81reg82regregregregregwirewireregregwirewireassignSclUp=(!SclIn)&&(Scl!=assignSclNp=( SclIn)&&(Scl==1'b0);assign =(MScl==1'b0)?1'b0:assignSda =(RSda==1'b0)?1'b0:1'bz;102assignIsBusy=Busy; always@(posedgeClk)if(!Rst)beginRdData<=1'b0;IsDone<=1'b0;elseif(BitC1==4'd8)beginRdData<=DataOut;IsDone<=1'b1;endelsebeginRdData<=RdData;IsDone<=1'b0;end always@(posedgeClk)if(!Rst Busy<=1'b0;BusyD1<=1'b0;elseBusyD1<=if(DetcSta||IsRsta||IsSta)Busy<=1'b1;elseif(DetcStp&&(s2==MScl_IDLE))Busy<= always@(posedgeClkif(!Rst)beginIsABL<=1'b0;elseif(IsABLRst)IsABL<=0;elseif((BusyD1&&GenSta)||((DetcStpD1)&&(!GenStp)))IsABL<=1'b1; 129/*******GenerateStartorStopbit always@(posedgeClkif(!Rst)beginGenSta<=1'b0;GenStp<=1'b0;DetcStpD1<=1'b0elseDetcStpD1<=if((!IsStaD1)&&(IsSta))GenSta<=1'b1;elseif(DetcSta)GenSta<=if((IsStaD1)&&(!IsSta))GenStp<=1'b1;elseif(DetcStp)GenStp<= always@(posedgeClkif(!RstbeginSdaIn<=1'b1;SclIn<=1'b1;IsStaD1<=1'b0;elseif(Scl==1'b0)SclIn<=1'b0;elseSclIn<=if(Sda==1'b0)SdaIn<=1'b0;elseSdaIn<=IsStaD1<= always@(posedgeClkif(!Rst||DetcSta)beginDetcStp<=1'b0;elseif((!SdaIn)&&(Sda!=1'b0beginif(Scl!=1'b0)DetcStp<=1'b1;elseDetcStp<=1'b0;always@(posedgeClkif(!Rst||s1==HEADER)beginDetcSta<=1'b0;elseif((SdaIn)&&(Sda==1'b0beginif(Scl!=1'b0)DetcSta<=1'b1;elseDetcSta<=1'b0;if(!Rsts1<=IDLE;IsRstaRst<=1'b0;SdaC1En<=1'b0;RSda<=1'b1;AckErr<=elseIsRstaRst<=case(s1 if((GenSta||IsRsta)&(RSda<=1;SdaC1En<=1'b1;if(SdaC1==8'd100)beginSdaC1En<=0;s1<=START;end StartbeginIsRstaRst<=1'b1;RSda<=0;if(SclNp)s1<=HEADER;HEADER://ShiftEightBitsif(BitC1<4'd8)RSda<=MSda;elses1<=ACK_HEADER;if(GenStp)s1<=RSda<=1'b1;if(SclUp)SdaC1En<=beginSdaC1En<=1'b0;if(Sda==1'b0)AckErr<=1'b0;elseAckErr<=1'b1;if(SclNp)if(!AckErr)begin if(DirSet)s1<=XMIT_DATA;elses1<=RCV_DATA;elsebegins1<=STOP;beginRSda<=1'b1;if(GenStp)s1<=STOP;elseif(BitC1==4'd8)s1<=ACK_DATA;endbeginRSda<=MSda;if(SclNp)beginif(IsRsta)s1<=IDLE;elses1<=RCV_DATA;endendif(BitC1<4'd8)RSda<=MSda;elses1<=if(GenStp)s1<=elseif(IsRsta)beginSdaC1En<=1'd0;s1<=IDLE;if(SclUp)SdaC1En<=SdaC1En<=1'b0;if(Sda==1'b0)AckErr<=1'b0;elseAckErr<=if(SclNpSdaC1En<=if(!AckErr)beginif(IsRsta)s1<=IDLE;elses1<=XMIT_DATA;elses1<=if(SclUp)SdaC1En<=if(SdaC1<STOP_HOLD_2)RSda<=elseif(SdaC1==STOP_HOLD_2)RSda<=elseif(SdaC1==STOP_HOLD)beginSdaC1En<=1'b0;s1<=IDLE;//masterSclalways@(posedgeClkif(!Rsts2<=MScl_IDLE;MScl<=1'b1;SclC1En<=elsecase(s2MScl<=1'b1;if(DetcSta)s2<= SclC1En<=1'b1;MScl<=if(SclC1==SclC1_HIGH)beginif(s1==IDLE)s2<=MScl_IDLE;elses2<= SclC1En<=1'b0; SclC1En<=1'b1;MScl<=if(SclC1==SclC1_LOW)beginSclC1En<=1'b0;s2<=MScl_HIGH;if(!Rst)beginMSda<=1'b1;elseif(s1==HEADER||s1==XMIT_DATA)MSda<=elseMSda<=wirewire 268wire269assign 271SHIFT8 284assignBitC1Ld=!BitC1En 290PULLUPU0(.O291PULLUPU1(.O292Module outputoutput output[7:0] [7:0] output14 [1:0]15 16 18 20 21 22 25wire26wire28 29wire31assign32assign33always@(posedgeClk)SckD1<=Sck; 35parameterBIT8=37always@(posedgeClk)//countshifted38if(SckEn&&SckUp)BitC<=BitC+1'b1;elseif(BitC==BIT8)BitC<=4'd0; 40assignMosi=DirSet?SftOut:1'b1;42always@(posedgeClk)//main43 s<=1'b0;IsDone<=1'b0;SckEn<=else0://IDLEbeginIsDone<=1'b0;IsDone<=1'b0;SckEn<=1'b0;if(IsSta)s<=1'b1;1://shift1'b1;s<= 5557//spiclockgenerator59parameterTSET=7'd1;always@(posedgeClk)//ShiftClockif(!Rst)beginSckC<=7'd0;Sck<=1'b0;SckState<=elsecase(SckStatebeginSckC<=7'd0;Sck<=1'd0;if(SckEn)SckState<=2;Sck<=1'b1;if(SckC>=TSET)beginSckState<=2;SckC<=7'd0;endelse<=SckC+0;0;Sck<=1'b0;if(SckC>=TSET) SckC<=7'd0;if(SckEn)SckState<=1;elseSckState elseSckC<=SckC+ 787880wire81 82 SlClk=DirSet?SckNp:83assignIsSpiLd=84SHIFT8 97Modulemodule output outputoutputoutput parameterIDLE=parameterHEADERw=parameterSTOPw=parameterHEADERr=parameterXMITr=parameterHEADERrr=parameterREADr=parameterWAIT= 25 [3:0]26 [18:0]27 [8:0]28 [7:0]29 [7:0]30 [7:0]32 33 34 35 36 37 39 40 42 [3:0] 43 [3:0]44 [3:0]45wire 47wire48assignRst=Cinit[8];50always@(posedge Clk)if(!Cinit[8])Cinit<=Cinit+1'b1;52wire53assignIsDoneUp=!IsDoneD1&&IsDone54always@(posedgeClk)IsDoneD1<=IsDone;56always if(!Rst) C1<=19'd0;s<=4'd0;read_buf<=8'd0;DirSet<=1'b0;WrData<=IsSta<=1'b0;IsAck<=1'b0;IsRsta<=elseif(IsRstaRst)IsRsta<=case(s 1://timemust>5MSif( 1://timemust>5MSif(C1[18]!=1'b1)<=C1+1'b1;elsebeginC1<=19'd0;s<=4'd2; if(!IsBusy)beginDirSet<=1'b1;WrData<=8'b1010_0010;IsSta<=1'b1;s<=4'd3;Led1<=4'd2;end if(IsDoneUp)beginWrData<=8'b0000_1000;s<=4'd4;Led1<=4'd3; if(IsDoneUp)beginWrData<=8'b0001_0011;s<=4'd5;Led1<=4;5://WriteDataif(IsDoneUp)beginIsSta<=1'b0;s<=4'd6;Led1<=4'd5;if(C1[18]!=1'b1)C1<=C1+1'b1;elsebeginC1<=19'd0;s<=4'd7; if(!IsBusy)beginWrData<=8'b1010_0010;IsSta<=1'b1;s<=4'd8;Led2<=1'b1; if(IsDoneUp)beginWrData<=8'b0000_1000;s<=4'd9;Led2<=4'd2; //Restartandwrite11://Read10://SetDirectionif(IsDoneUp)beginIsRsta<=1'b1;WrData<=11://Read10://SetDirectionDirSet<=1'd0;s<=4'd11;Led2<=4'd3; if(IsDoneUp)beginIsSta<=1'b0;IsAck<=1'b1;read_buf<=RdData;s<=4'd12;Led2<=4;end 12://Read if(Sw1&&!IsSta)s<= elses<= 9294I2C 113assign114assign Dpy4SDRAMFigure1:SDRAMmainTable1:SDRAMmainModuleFunctionSystemSystemSDRAMdataLEDdriveTable2:SDRAMModuleFunctionSDRAMmoduleSystemSDRAMmodulewriteSDRAMmodulereadSDRAMmodulehavefinishedSDRAMmoduleisbusyininitialDataneedtobewritenintosdramDataneedtobereadfromsdramSDRAMdata Figure2:SDRAMmoduleinnerTable3:SDRAMInitModuleFunctionSDRAMmoduleSystemSDRAMinitialmoduleinitSDRAMinitialmoduleinittaskSDRAMfunctionmoduletaskDataneedtobewritenintosdramDataneedtobereadfromsdramSDRAMdataTable5:SDRAMCtrModuleFunctionSDRAMmoduleSystemSDRAMmodulewriteSDRAMmodulereadSDRAMmodulehavefinishedSDRAMmodulebusyininitialSDRAMinitialmoduleinittaskSDRAMfunctionmoduletaskSDRAMinitialmoduleinitSDRAMdataSDRAM64MSDRAM,64MSDRAM可以有三種配置模式.如下圖描述Figure3:SDRAMpinsand64MSDRAM4BANKBANK16M8bitsBANK4096512列組成。我們是16bits數(shù)據(jù)線，如下圖所示。Figure4:16Megx4SDRAMS1INHIBITNOP100usS2：PRECHARGE預充電命令S5：SDRAM初始化完成SDRAMFigure5:ModeSDRAM的操作比較復雜，有很多種模式，如果要搞清楚，請看技術手冊，我們這里是以SDRAMSDRAMInit模塊中SDRAM必須不停的進行刷新以防止數(shù)據(jù)的丟失，SDRAM15.625μs內被刷新。下面看下SDRAM的刷新時序。Figure7:AutorefreshFigure7:AutorefreshS1ACTIVEBANKROWS2：等待RCD的時間，至少15nsS4：等待CAS延遲Figure8:SINGLEREAD–WITHAUTO本設計，采用了singlereadwithautoprecharge模式，每次操作我們只一個字節(jié)。S1ACTIVEBANKROWS2：等待RCD的時間，至少15nsDQM，等待trp時間15nsSDRAM我們可以用if()else語句設置優(yōu)先級。這里是SDRAM50MHZ，為了滿足時序要求，我們把系統(tǒng)時鐘分頻為25MHZ，來操作SDRAM。module outputoutput outputoutput16 parameterT15US=regalways@(posedgeClkornegedgeRst if(!Rst beginC1<=22'd0;IsRef<=1'b0; elseif(IsRef&&IsArDone beginC1<=22'd0;IsRef<=1'b0; elseif(C1==T15US beginC1<=22'd0;IsRef<=1'b1; elseif(!IsRef C1<=C1+ 34 regreg[2:0]IsFunSta;//[2]AutoRefresh,[1]ReadAction,[0]Writeregregregalwaysalways@(posedgeClkornegedgeRst)if(!Rst)s<= IsInitSta<=1'b0;//InitialSDRamat <= <=case(s 0://IDLE if( )beginIsFunSta<=3'b100;s<=3'd1; elseif(IsRdEn)beginIsFunSta<=3'b010;s<=3'd2;end//Write elseif(IsWrEn)beginIsFunSta<=3'b001;s<=3'd2;end//Read1://AutoRefreshif(IsArDone)beginIsFunSta<=3'd0;s<=3'd0;end 2://Func