SPIandJTAG第1頁SerialPeripheralInterface(SPI)Theserialperipheralinterface(SPI)allowstheMPC8272toexchangedatabetweenotherMPC8272chipstheMPC860theMC68360,theMC68302,theM68HC11andM68HC05microcontrollerEEPROMreal-timeclocksA/DconvertersISDNdevices.TheSPIisafull-duplex,synchronous,character-orientedchannelthatsupportsafour-wireinterface(receive,transmit,clockandslaveselect).8272SPIcontrollerSPIBRGBRGclockSPISELSPIMOSISPIMISOSPICLK第2頁SPIasamasterdeviceGPIO第3頁HowSPImasterworkCorewritedataintoTXbufferCoresetTXBD[R]PrepareoneormoreRxBDCoresetSPCOM[STR]DataoutonSPIMOSIDatainonSPIMISODatawrittenintoRxBufferThewholebuffersendout?ENDYESNO第4頁SPIasslavedevice8272SPICLKSPICLKSPISEL#SPISEL#SPIMOSISPIMISOSPIMISOSPIMOSINotaGPIOSPISlaveSPImaster第5頁HowSPIslaveworkCorewritedataintoTXbufferCoresetTXBD[R]PrepareoneormoreRxBDCoresetSPCOM[STR]DataoutonSPIMOSIDatainonSPIMISODatawrittenintoRxBufferTheTxbuffersendoutorRxbufferisfull?InterruptYESSPISEL#isassertedNOYESYES第6頁SPIworksinmulti-mastermode第7頁SPIclocklimitationAsmaster,maximumclockrateis?systemclock.Asslave,maximumclockrateis1/2systemclock.ThemaximumsustaineddataratethattheSPIsupportsisSYSTEMCLK/50.However,theSPIcantransferasinglecharacteratmuchhigherrates—SYSTEMCLK/4inmastermodeandSYSTEMCLK/2inslavemode.Gapsshouldbeinsertedbetweenmultiplecharacterstokeepfromexceedingthemaximumsustaineddatarate.第8頁SPImemorystructure

SPIconfigurationregistersresideinDPRAMfromIMMR+0x11AA0toIMMR+0x11AA8

SPIparameterRAMpointerisprogrammedinIMMR+0x89FC.第9頁SPIModeRegister(SPMODE)(1/2)第10頁SPIModeRegister(SPMODE)(2/2)

第11頁SPIcommandregister(SPCOM)andSPIcommands(CPCR)

SPCOM[STR]:Starttransmit.STRisclearedautomaticallyafteronesystemclockcycle.

INITTXPARAMETERS:InitializesalltransmitparametersintheparameterRAMtotheirresetstateandshouldbeissuedonlywhenthetransmitterisdisabled.CloseRXBD:ForcestheSPIcontrollertoclosethecurrentRxBDandusethenextBDforsubsequentlyreceiveddata.Ifthecontrollerisnotreceivingdata,noactionistaken.Usethiscommandtoextractdatafromapartiallyfullbuffer.INITRXPARAMETERS:InitializesallreceiveparametersintheparameterRAMtotheirresetstate.Shouldbeissuedonlywhenthereceiverisdisabled.INITRXandTXPARAMETERS:TheINITTXANDRXPARAMETERScommandcanalsobeusedtoresetboththeTxandRxparameters.第12頁SPIparameterRAM(1/2)第13頁SPIparameterRAM(2/2)第14頁SPImasterinitializationexample(1/2)1.ConfigureportDtoenableSPIMISO,SPIMOSI,SPICLKandSPISEL.2.ConfigureaparallelI/OsignaltooperateastheSPIselectoutputsignalifneeded.3.Inaddress0x89FC,assignapointertotheSPIparameterRAM.4.WriteRBASEandTBASEintheSPIparameterRAMtopointtotheRxBDandTxBDtablesinthedual-portRAM.AssumingoneRxBDfollowedbyoneTxBDatthebeginningofthedual-portRAM,writeRBASEwith0x0000andTBASEwith0x0008.5.WriteRFCRandTFCRwith0x10fornormaloperation.6.WriteMRBLRwiththemaximumnumberofbytesperRxbuffer.Forthiscase,assume16bytes,soMRBLR=0x0010.7.InitializetheRxBD.AssumetheRxbufferisat0x0000_1000inmainmemory.Write0xB000toRxBD[StatusandControl],0x0000toRxBD[DataLength](optional),and0x0000_1000toRxBD[BufferPointer].第15頁SPImasterinitializationexample(1/2)

8.InitializetheTxBD.AssumetheTxbufferisat0x0000_2023inmainmemoryandcontainsfive8-bitcharacters.Write0xB800toTxBD[StatusandControl],0x0005toTxBD[DataLength],and0x0000_2023toTxBD[BufferPointer].9.ExecutetheINITRXANDTXPARAMETERScommandbywriting0x2541_0000toCPCR.10.Write0xFFtoSPIEtoclearanypreviousevents.11.Write0x37toSPIMtoenableallpossibleSPIinterrupts.12.Write0x0370toSPMODEtoenablenormaloperation(notloopback),mastermode,SPIenabled,8-bitcharacters,andthefastestspeedpossible.13.SetSPCOM[STR]tostartthetransfer.第16頁JTAGsignalsTCKAtestclockinputtosynchronizethetestlogicTMSAtestmodeselectinput(withaninternalpull-upresistor)thatissampledontherisingedgeofTCKtosequencetheTAPcontroller’sstatemachineTDIAtestdatainput(withaninternalpull-upresistor)thatissampledontherisingedgeofTCKTDOAdataoutputthatcanbethree-statedandactivelydrivenintheshift-IRandshift-DRcontrollerstates.TDOchangesonthefallingedgeofTCKTRSTAnasynchronousresetwithaninternalpull-upresistorthatprovidesinitializationoftheTAPcontrollerandotherlogicrequiredbythestandard第17頁HowtoconnectadebuggerbyJTAG/COPCOP/JTAGportconnectorBoard16wiresflatcableEthernet/parallel/USB/RS232debuggerHost第18頁HowtohandletheJTAGpinsinschematic1TDOTestDataOutNone2QACKQuiescentAcknowledgementQACKisnotbroughtoutoftheG2core.LeaveunconnectedtiedirectlytoGND.3TDITestDataInAdd10Kpull-uptoVDDH=3.3V.4TRSTTestResetConnecttoMPC8260TRSTsignal.Adda1Kpull-downtoGND.ThisisdoneinsidethechipbyconnectingTRSTtoPORESET.5QREQQuiescentRequestMaybeoptionallyconnectedtoMPC8260QREQsignal.Add10Kpull-uptoVDDH=3.3Vinallcases.6V3.3I/OPowerSupplyConnecttoMPC8260I/OVoltageVDDHthrougha1Kcurrentlimitingresistor7TCKTestClockAdd10Kpull-uptoVDDH=3.3V.8,10N.C.NoConnectLeaveunconnected.9TMSTestModeSelectAdd10Kpull-uptoVDDH=3.3V.11SRESETSoftResetConnecttotheSRESETandHRESETsignalsontheMPC8260usingopencircuitgates.RefertoSection1.8.1,“MergingResetSignals”13HRESETHardReset14“KEY”MechanicalKeyingPinshouldberemoved.15CKSTP_OUTCheckStopOutputAdd10Kpull-uptoVDDH=3.3V.12,16GNDSystemGroundPlaneConnecttodigitalground.TRSTnotpulleddown–FailtobootupTRSTpulleddownby510ohmresistor–FailtoconnectwithdebuggerTDIpu