1DesignCompilerforChipSynthesis

2AgendaIntroductiontoSynthesisSetup,LibraryandObjectsTimingandAreaEnvironmentalAttributesOptimizationCompileStrategies3AgendaIntroductiontoSynthesisSetup,LibraryandObjectsTimingandAreaEnvironmentalAttributesOptimizationCompileStrategies4DesignFlowYouarehere!5(read)(compile)6IntroductiontoDCTheDesignCompilerproductisthecoreoftheSynopsyssynthesissoftwareproducts.ItcomprisestoolsthatsynthesizeyourHDLdesignsintooptimizedtechnology-dependent,gate-leveldesigns.Itsupportsawiderangeofflatandhierarchicaldesignstylesandcanoptimizebothcombinationalandsequentialdesignsforspeed,areaandpower.

7SynthesisIsConstraint-DrivenYousetthegoals(throughconstraints).Synthesistooloptimizesthedesigntomeetyourgoals

flatten8SynthesisIsPath-BasedDesignCompilerusesStaticTimingAnalysis(STA)tocalculatethetimingofthepathsinthedesignSynthesistoolsummaryASICsynthesistools:Synopsys:DesignCompiler,DesignVision,DesignAnalyzerMagma:BlastFusionCadence:BuildGatesFPGAsynthesistools:Synplicity:SymplifyXilinx:ISEAltera:Quartus910AgendaIntroductiontoSynthesisSetup,LibraryandObjectsTimingandAreaEnvironmentalAttributesOptimizationCompileStrategiesSetup,LibraryandObjectsProjectDirectoryPreparation11.synopsys_dc.setupSoftwareinstalldirectoryUser’sGeneralSetupdirectoryUser’sSpecificProjectSetupdirectory:三個setup文件依次執(zhí)行,后者可以覆蓋前者的定義Commandsin.synopsys_dc.setupareexecutedupontoolstartup.synopsys_dc.setupsearch_pathtarget_librarylink_librarysymbol_library1314TargetLibraryThetargetlibraryisthelibraryusedbyDCforbuildingacircuitduringcompileDuringmapping,DCwill:1.Choosefunctionally-correctgatesfromthislibrary2.Calculatethetimingofthecircuitusingvendor-suppliedtimingdataforthesegates15LinkLibraryUsedtoresolveleaf-cellsandsubdesignreferenceSymbolLibraryThesymbol_librarysystemvariableholdsthenameofthelibrary,containinggraphicalrepresentationofthecellsinthetechnologylibrary.16DesignObject171819The“get_*”CommandThe“get_*”commandsreturnobjectsinthecurrent_designObjectsmaybeusedtogetherwith*wildcard:

set_load5[get_portsaddr_bus*]20“get_*”Commandget_cellsget_clocksget_designsget_netsget_pinsget_ports…21OtherHandyListCommandsListallinputandinoutportsofthecurrentdesigns:dc_shell-t>all_inputsListalloutputandinoutportsofthecurrentdesigns:dc_shell-t>all_outputsListalldesigninDCmemorydc_shell-t>get_design*22AgendaIntroductiontoSynthesisSetup,LibraryandObjectsTimingandAreaEnvironmentalAttributesOptimizationCompileStrategies23SpecifyinganAreaGoaldc_shell-t>current_designPRGRM_CNT_TOPdc_shell-t>set_max_area0RelatedcommandsinDC:compile–area_effortnone|low|medium|highreport_area24TimingGoals:SynchronousDesigns25DefiningaClockYouMUSTDefine:1.ClockSource(portorpin)2.ClockPeriodYoumayalsodefine:DutyCycleOffset/SkewClockNameClock26ModelingClockTreesDesignCompilerisNOTusedforsynthesisoftheclocktreeClocktreesynthesisisusuallydonebyPRtools.27ModelingUncertaintyonClockEdgesUncertaintyisthedelaydifferencebetweentheclocknetworkbranches(commonlycalledclockskew)ThismayalsobeusedtoaccountforPLLjitter28ModelSourceLatencycreate_clock–period10[get_portsCLK]29InputDelay30ConstrainingtheInputPaths31OutputDelay32ConstrainingtheOutputPaths33VerifythatconstraintsAftersettingconstraints,verifythattherearenoremainingunconstrainedpaths:Makecertaintheconstraintsyouappliedwereappliedcorrectly:34AgendaIntroductiontoSynthesisSetup,LibraryandObjectsTimingandAreaEnvironmentalAttributesOptimizationCompileStrategies35DescribingEnvironmentalAttributes36ModelingCapacitiveLoadInordertoaccuratelycalculatethetimingofanoutputcircuit,DCneedstoknowthetotalcapacitancedrivenbytheoutputcellsset_loadallowsyoutospecifytheexternalcapacitiveloadonports(inputsoroutputs):1.Bydefault,DCassumesthattheexternalloadonportsis02.Youcanspecifysomeotherconstantvalue3.Theload_ofcommandcanbeusedtospecifytheexternalloadasthepinloadofacellinyourtechlibrary37set_loadExamplesset_load5[get_portsOUT1]set_load[load_ofmy_lib/AN2/A][get_portsOUT1]set_load[expr[load_of\my_lib/inv1a0/A]*3][get_portsOUT1]load_oflib/cell/pin38ModelingInputDriveStrengthInordertoaccuratelycalculatethetimingofaninputcircuit,DCneedstoknowthetransitiontimeofthesignalarrivingattheinputportset_driving_cellallowsyoutospecifyarealisticexternalcelldrivingtheinputports:1.Bydefault,DCassumesthattheexternalsignalhasatransitiontimeof02.PlacingadrivingcellontheinputportscausesDCtocalculatetheactual(non-zero)transitiontimeontheinputsignalasthoughthespecifiedlibrarycellwasdrivingit39set_driving_cellExamplesset_driving_cell\-lib_cellFD1\-pinQ\[get_portsIN1]40OperatingConditionsLibrarycellsareusuallycharacterizedusing“nominal”voltageandtemperature.Operatingconditionscanbeplacedonyourdesignbyusingtheset_operating_conditions41SpecifyOperatingConditionUsuallythelibraryspecifiesadefaultoperatingconditionUsereport_lib

libnametolisttheoperatingconditionsTosetoperatingconditionsenter:42WireLoadModelAwireloadmodelisanestimateofanet’sRCparasiticsbasedonthenet’sfanout43SpecifyingWireLoadsinDCManualmodelselectionAutomaticmodelselection(defaultisTRUE)

44WireLoadModelMode45DesignRuleConstraints(DRC)set_max_transitionset_max_capacitanceset_max_fanout46report_timingreport_timingreport_timing>./rpt/timing.rptredirect./rpt/timing.rpt{report_timing}47report_timingpathpathgroupsetupcheckIndividualContributiontoPathDelayTotalPathDelayCalculationConstraintmeetorviolate4849AgendaIntroductiontoSynthesisSetup,LibraryandObjectsTimingandAreaEnvironmentalAttributesOptimizationCompileStrategies50ThreePhasesofCompileOptimizationcanoccurateachofthreelevels51ArchitecturalOptimization52ImplementationSelectionMultiplearchitecturesforeachoperatorallowDCtoevaluatespeed/areatradeoffsandchoosethebestimplementation53WhatisDesignWareLibraryCollectionofIPblocksandDatapathcomponents

Technologyindependent,pre-verified,reusable,parameterizable,synthesizableAccessingtheRightComponent

OperatorInferencing:+,-,*,>,=,<FunctionalInferencing:DWF_multi_tc,DWF_div_unsSynopsyssyntheticlibraryfilesresideinthedirectory:$SYNOPSYS/libraries/synBydefault,thevariablesynthetic_libraryisempty54SharingCommonSubexpressionsDCcan“share”commonmathematicalsubexpressions.55CodingtoForceSharingRememberHDLcodingcanforceaspecifictopologytobesynthesizedToforceasharedtopologydirectly:temp<=A+B;SUM1<=temp+C;SUM2<=temp+D;SUM3<=temp+E;56ResourceSharing:Exampleif(SEL=‘1’)thenSUM<=A+B;elseSUM<=C+D;endif;GiventhefollowingHDLdescription,twodifferentstructuresmightbesynthesized:57OperatorReorderingDCcanautomaticallyreorderarithmeticoperatorstoproducethefastestdesignsCodingstylecanforceaparticularorderZ=((B+C)+D)+Late_A58Logic-LevelOptimization59StructuringTheuseofcommonsubexpressionstoreducelogicBeforestructuring:f0=a*b+a*cf1=b+c+df2=b’*c’*eAfterstructuring:f0=a*t0f1=t0+df2=t0’*et0=b+c60FlatteningThereductionofcombinationallogicpathstoatwo-level,sum-of-products(SOP)circuit61Structuringvs.FlatteningStructuringcreatesintermediatestructurestoimplementdesignIsconstraint-basedCanhelpbothareaandspeedofadesignFlatteningRemovesIntermediatestructures-reducesdesigntoSOPIsdoneindependentofconstraintsCanbeveryarea-intensiveNoguaranteethatflatteningwillactuallymaptoatwo-levelSOP(possiblelibrarylimitations)62Gate-LevelOptimization63CombinationalMappingTheprocessofusinggatesfromthetargetlibrarytogenerateadesignthatmeetstimingandareagoals64SequentialMappingTh