IPC-6012E

2020-March

QualificationandPerformanceSpecificationforRigid

PrintedBoards

SupersedesIPC-6012DSeptember2015

AninternationalstandarddevelopedbyIPC

AssociationConnectingElectronicsIndustries

?

IPC-6012E

QualificationandPerformanceSpecificationforRigidPrintedBoards

DevelopedbytheRigidPrintedBoardPerformanceSpecificationsTaskGroup(D-33a)oftheRigidPrintedBoardCommittee(D-30)ofIPC

Supersedes:

IPC-6012D-September2015IPC-6012C-April2010

IPC-6012BwithAmendment1-July2007

IPC-6012B-August2004

IPC-6012AwithAmendment1-July2000

IPC-6012A-October1999IPC-6012-July1996

IPC-RB-276-March1992

Usersofthispublicationareencouragedtoparticipateinthedevelopmentoffuturerevisions.

Contact:

IPC

March2020 IPC-6012E

TableofContents

SCOPE 1

StatementofScope 1

Purpose 1

SupportingDocumentation 1

PerformanceClassificationandType 1

Classification 1

PrintedBoardType 1

SelectionforProcurement 1

Material,PlatingProcessandSurfaceFinish 3

TermsandDefinitions 4

Back-Drilling 4

Stub(PlatedHole) 4

HighDensityInterconnects(HDI) 4

Microvia 5

DesignData 5

Interpretation 5

Presentation 5

DesignDataProtection 5

RevisionLevelChanges 5

APPLICABLEDOCUMENTS 6

IPC 6

JointIndustryStandards 8

Federal 8

OtherPublications 8

AmericanSocietyforTestingandMaterials 8

UnderwritersLab 8

NationalElectricalManufacturers

Association 8

AmericanSocietyforQuality 8

AMS 8

AmericanSocietyofMechanicalEngineers 8

REQUIREMENTS 9

General 9

Materials 9

LaminatesandBondingMaterial 9

ExternalBondingMaterials 9

OtherDielectricMaterials 9

MetalFoils 9

MetalPlanes/Cores 9

BaseMetallicPlatingDepositionsandConductiveCoatings 9

SurfaceFinishDepositionsandCoatings–MetallicandNon-Metallic 10

PolymerCoating(SolderMask) 13

FusingFluidsandFluxes 13

MarkingInks 13

HoleFillInsulationMaterial 13

HeatsinkPlanes,External 13

ViaProtection 14

EmbeddedPassiveMaterials 14

VisualExamination 14

Edges 14

LaminateImperfections 14

PlatingandCoatingVoidsintheHole 15

LiftedLands 15

Marking 15

Solderability 16

PlatingAdhesion 16

EdgePrintedBoardContact,Junctionof

GoldPlatetoSolderFinish 16

Back-DrilledHoles 17

Workmanship 17

PrintedBoardDimensionalRequirements 17

HoleSize,HolePatternAccuracyand

PatternFeatureAccuracy 17

AnnularRingandBreakout(External) 17

BowandTwist 19

ConductorDefinition 19

ConductorWidthandThickness 20

ConductorSpacing 20

ConductorImperfections 20

ConductiveSurfaces 20

StructuralIntegrity 22

ThermalStressTesting 23

RequirementsforMicrosectioned

CouponsorPrintedBoards 24

SolderMaskRequirements 39

SolderMaskCoverage 39

SolderMaskCureandAdhesion 39

SolderMaskThickness 40

ElectricalRequirements 40

DielectricWithstandingVoltage 40

ElectricalContinuityandIsolation

Resistance 40

Circuit/PlatedHoleShortstoMetal

Substrate 40

MoistureandInsulationResistance(MIR) 40

v

IPC-6012E March2020

Cleanliness 41

CleanlinessPriortoSolderMask

Application 41

CleanlinessAfterSolderMask,Solder,orAlternativeSurfaceCoatingApplication 41

CleanlinessofInnerLayersAfterOxideTreatmentPriortoLamination 41

SpecialRequirements 41

Outgassing 41

FungusResistance 41

Vibration 41

MechanicalShock 41

ImpedanceTesting 41

CoefficientofThermalExpansion(CTE) 42

ThermalShock 42

SurfaceInsulationResistance

(AsReceived) 42

MetalCore(HorizontalMicrosection) 42

ReworkSimulation 42

BondStrength,UnsupportedComponent

HoleLand 42

DestructivePhysicalAnalysis 42

PeelStrengthRequirements(ForFoil

LaminatedConstructionOnly) 42

DesignDataProtection 42

PerformanceBasedTestingforMicroviaStructures–StructuralIntegrityDuring

ThermalStress 43

Repair 43

CircuitRepairs 43

Rework 43

QUALITYASSURANCEPROVISIONS 43

General 43

Qualification 43

SampleTestCoupons 43

AcceptanceTests 44

C=0ZeroAcceptanceNumberSampling

Plan 44

RefereeTests 44

QualityConformanceTesting 44

CouponSelection 45

NOTES 50

OrderingData 50

SupersededSpecifications 50

APPENDIXA 51

Figures

Figure1-1 ExampleofaBack-DrilledHole

(NotToScale) 4

Figure1-2 ExampleofaShallowBack-Drill 4

Figure1-3 MicroviaDefinition 5

Figure3-1 AnnularRingMeasurement(External) 19

Figure3-2 Breakoutof90°and180° 19

Figure3-3 ExternalConductorWidthReduction 19

Figure3-4 ExampleofIntermediateTargetLandinaMicrovia 19

Figure3-5 RectangularSurfaceMountLands 20

Figure3-6 RoundSurfaceMountLands 21

Figure3-7 PrintedBoardEdgeConnectorLands 21

Figure3-8 PlatedHoleMicrosection(Grinding/

Polishing)Tolerance 23

Figure3-9 AnExampleofPlatingtoTargetLandSeparation 23

Figure3-10 CopperCrackDefinition 26

Figure3-11 SeparationsatExternalFoil 26

Figure3-12 PlatingFolds/Inclusions–MinimumMeasurementPoints 26

Figure3-13 MicrosectionEvaluationLaminate

Attributes 27

Figure3-14 MeasurementforEtchback 27

Figure3-15 MeasurementforDielectricRemoval 28

Figure3-16 MeasurementforNegativeEtchback 28

Figure3-17 AnnularRingMeasurement(Internal) 29

Figure3-18 MicrosectionRotationsforBreakout

Detection 29

Figure3-19 ComparisonofMicrosectionRotations 29

Figure3-20 ExampleofNon-ConformingDielectricSpacingReductionDuetoBreakoutat

MicroviaTargetLand 30

Figure3-21 SurfaceCopperWrapMeasurementfor

FilledHoles(OverFoil) 30

Figure3-22 SurfaceCopperWrapMeasurementfor

FilledHoles(OverLaminate) 31

Figure3-23 SurfaceCopperWrapMeasurementfor

Non-FilledHoles 31

Figure3-24 WrapCopper(Acceptable) 31

Figure3-25 WrapCopperRemovedbyExcessiveProcessing,e.g.,Sanding/Planarization/

Etching(NotAcceptable) 32

Figure3-26 CopperCapThickness 33

Figure3-27 CopperCapFilledViaHeight(Bump) 33

Figure3-28 CopperCapDepression(Dimple) 33

Figure3-29 CopperCapPlatingVoids 33

Figure3-30 NonconformingViaFillBetweenCopper

CapPlatingLayers 33

Figure3-31 AcceptableViaFillBetweenCopperCap

PlatingLayers 33

Figure3-32 ExampleofAcceptableVoidinginaCap

Plated,CopperFilledVia 34

vi

March2020 IPC-6012E

Figure3-33 ExampleofAcceptableVoidinginaCopperFilledMicroviawithoutCapPlating 34

Figure3-34 ExampleofNonconformingVoidinaCapPlated,CopperFilledMicrovia 34

Figure3-35 ExampleofNonconformingVoidina

CopperFilledMicrovia 34

Figure3-36 MicroviaContactDimension 35

Figure3-37 ExclusionofSeparationsinMicrovia

TargetLandContactDimension 35

Figure3-38 UnintendedPiercingofMicroviaTarget

Land(LaserDrilled) 35

Figure3-39 IntentionalPiercingofMicroviaTarget

Land(MechanicallyDrilled2) 35

Figure3-40 Overhang 37

Figure3-41 MetalCoretoPTHSpacing 37

Figure3-42 MeasurementofMinimumDielectric

Spacing 38

Figure3-43 FillMaterialinBlind/ThroughVias

WhenCapPlatingNotSpecified 38

Figure3-44 VoidinFillMaterialatHoleWallInterface 38

Tables

Table1-1 TechnologyAdders 2

Table1-2 DefaultRequirements 3

Table3-1 MetalPlanes/Cores 9

Table3-2 MaximumLimitsofSnPbSolderBathContaminant 10

Table3-3 SurfaceFinishandCoatingRequirements 12

Table3-4 SurfaceandHoleCopperPlatingMinimumRequirementsforBuriedVias>2Layers,Through-Holes,andBlindVias 13

Table3-5 SurfaceandHoleCopperPlatingMinimumRequirementsforMicrovias

(BlindandBuried) 13

Table3-6 SurfaceandHoleCopperPlatingMinimumRequirementsforBuriedCores(2layers) 13

Table3-7 PlatingandCoatingVoidsintheHole 15

Table3-8 EdgePrintedBoardContactGap 17

Table3-9 MinimumAnnularRing 18

Table3-10PlatedHoleIntegrityAfterStress 25

Table3-11CapPlatingRequirementsforFilledHoles 32

Table3-12MicroviaContactDimension(LaserDrilled) 35

Table3-13MicroviaContactDimension

(MechanicallyDrilled) 35

Table3-14InternalLayerFoilThicknessafter

Processing 36

Table3-15ExternalConductorThicknessafter

Plating 37

Table3-16SolderMaskAdhesion 40

Table3-17DielectricWithstandingVoltages 40

Table3-18InsulationResistance 40

Table4-1 QualificationTestCoupons 44

Table4-2 C=0SamplingPlanperLotSize 45

Table4-3 AcceptanceTestingandFrequency 46

Table4-4 QualityConformanceTesting 50

vii

March2020 IPC-6012E

QualificationandPerformanceSpecificationforRigidPrintedBoards

SCOPE

StatementofScopeThisspecificationestablishesanddefinesthequalificationandperformancerequirementsforthefabricationofrigidprintedboards.

PurposeThepurposeofthisspecificationistoproviderequirementsforqualificationandperformanceofrigidprintedboardsbasedonthefollowingconstructionsand/ortechnologies.Theserequirementsapplytothefinishedproductunlessotherwisespecified:

Single-sided,double-sidedprintedboardswithorwithoutplated-throughholes(PTHs).

MultilayerprintedboardswithPTHswithorwithoutburied/blindvias/microvias.

Active/passiveembeddedcircuitryprintedboardswithdistributivecapacitiveplanesand/orcapacitiveorresistivecomponents.

Metalcoreprintedboardswithorwithoutanexternalmetalheatframe,whichmaybeactiveornon-active.

SupportingDocumentationIPC-A-600,whichcontainsfigures,illustrationsandphotographsthatcanaidinthevisualizationofexternallyandinternallyobservableacceptable/nonconformingconditions,maybeusedinconjunctionwiththisspecificationforamorecompleteunderstandingoftherecommendationsandrequirements.

PerformanceClassificationandType

ClassificationThisspecificationestablishesacceptancecriteriafortheperformanceclassificationofrigidprintedboardsbasedoncustomerand/orend-userequirements.PrintedboardsareclassifiedbyoneofthreegeneralPerformanceClassesasdefinedinIPC-6011.

RequirementDeviationsRequirementsdeviatingfromtheseheritageclassificationsshallbeasagreedbetweenuserandsupplier(AABUS).

SpaceRequirementDeviationsSpaceperformanceclassificationdeviationsareprovidedintheIPC-6012ES

Addendumandareapplicablewhentheaddendumisspecifiedwithintheprocurementdocumentation.

PrintedBoardTypePrintedboardswithoutPTHs(Type1)andwithPTHs(Types2-6)areclassifiedasfollowsandmayincludetechnologyaddersasdescribedinTable1-1:

Type1—Single-SidedPrintedBoard

Type2—Double-SidedPrintedBoard

Type3—MultilayerPrintedBoardwithoutblindorburiedvias

Type4—MultilayerPrintedBoardwithblindand/orburiedvias(mayincludemicrovias)

Type5—MultilayermetalcorePrintedBoardwithoutblindorburiedvias

Type6—MultilayermetalcorePrintedBoardwithblindand/orburiedvias(mayincludemicrovias)

SelectionforProcurementPerformanceClassshallbespecifiedintheprocurementdocumentation.

Theprocurementdocumentationshallprovidesufficientinformationtofabricatetheprintedboardandensurethattheuserreceivesthedesiredproduct.InformationthatshouldbeincludedintheprocurementdocumentationistobeinaccordancewithIPC-2611andIPC-2614.

Theprocurementdocumentationshallspecifythethermalstresstestmethodtobeusedtomeettherequirementof3.6.1.Selectionshallbefromthosedepictedin,and.Ifnotspecified(see5.1),thedefaultshallbeperTable1-2.

1

IPC-6012E March2020

WhentestedinaccordancewithIPC-TM-650,Method,themaximumpercentageofcuredsoldermaskliftingfromtheGcouponorprintedboardshallbeinaccordancewithTable3-16.

Table3-16SolderMaskAdhesion

MaximumPercentageLossAllowed

Surface

Class1

Class2

Class3

BareCopper

10

5

0

GoldorNickel

25

10

5

BaseLaminate

10

5

0

MeltingMetals(Tin-leadplating,fusedtin-lead,andbrightacid-tin)

50

25

10

3.7.3SolderMaskThicknessAnyrequirementforthemeasurementofsoldermaskthicknessshallbeAABUS.Ifathicknessmeasurementisrequired,instrumentalmethodsmaybeusedorassessmentmaybemadeusingamicrosectionoftheparallelconductorsontheEcouponorDestructivePhysicalAnalysis(DPA)(see3.10.12,thermalstressnotrequired).Foradditionalguidanceonsoldermaskthicknessmeasurementoptions,seetheIPC-6012AutomotiveAddendum.

ElectricalRequirementsWhentestedasspecifiedinTable4-3andTable4-4,theprintedboardsshallmeettheelec-tricalrequirementsdetailedinthefollowingparagraphs.

DielectricWithstandingVoltageApplicabletestcouponsorprintedboardsshallmeettherequirementsofTable3-17,withoutflashover,orbreakdownbetweenconductors,orconductorsandlands.ThedielectricwithstandingvoltagetestshallbeperformedinaccordancewithIPC-TM-650,Method2.5.7.Thedielectricwithstandingvoltageshallbeappliedbetweenallcommonportionsofeachconductorpatternandadjacentcommonportionsofeachconductorpattern.Thevolt-ageshallbeappliedbetweenconductorpatternsofeachlayerandtheelectricallyisolatedpatternofeachadjacentlayer.Forembeddedpassivedevicecapacitormaterials,thedielectricwithstandingvoltageforadjacentplanelayersthatarenotelec-tricallycommonshallbeperIPC-6017.

Table3-17

DielectricWithstandingVoltages

Class1

Class2andClass3

VoltageforSpacing80pm[3,150pin]orgreater

Norequirement

(500+15-0)V(dc)

VoltageforSpacinglessthan80pm[3,150pin]

Norequirement

(250+15-0)V(dc)

Time

Norequirement

30sec+3,-0

ElectricalContinuityandIsolationResistanceFinishedprintedboardsshallbetestedinaccordancewithIPC-9252.Electricalcontinuityandisolationresistancetestingofblindandburiedstructuresisnotrequiredforinprocesschecks.

Circuit/PlatedHoleShortstoMetalSubstratePrintedboardsshallbetestedinaccordancewith3.8.1exceptthatpolarizingvoltageof(500+15-0)V(dc)shallbeappliedbetweenconductorsand/orlandsandthemetalsubstrate(heatsinkorcore)inamannersuchthateachconductor/landareaistested(e.g.,usingametallicbrushoraluminumfoil).Theprintedboardshallbecapableofwithstanding(500+15-0)V(dc)betweencircuitry/platedholesandthemetalcoresub-strates.Thereshallbenoflashoverordielectricbreakdown.

MoistureandInsulationResistance(MIR)Testcouponsshallbetestedinaccordancewiththeprocedureoutlinedbelow.Thetestcouponshallnotexhibitsubsurfaceimperfectionsinexcessofthatallowedin3.3.2.InsulationresistanceshallmeettheminimumrequirementsshowninTable3-18(at(500+15-0)V(dc)).Non-componentflushprintedboardsshallhaveaminimumrequirementof50MOforallclasses.

Table3-18InsulationResistance

Class1

Class2

Class3

Asreceived1

Maintainelectricalfunction

500MQ

500MQ

Afterexposuretomoisture

Maintainelectricalfunction

100MQ

500MQ

Note1.ThismeasurementistakenafterconformalcoatingmaterialhasbeenappliedtothetestcouponinaccordancewithIPC-TM-650,Method2.6.3.

ThemoistureandinsulationresistanceforprintedboardsshallbeperformedinaccordancewithIPC-TM-650,Method2.6.3.ConformalcoatinginaccordancewithIPC-CC-830shallbeappliedtotheexternalconductorspriortochamberexposure.Finalmeasurementsshallbemadeatroomtemperaturewithintwohoursafterremovalfromthetestchamber.Alllayers

40

IPC-6012E March2020

Figure3-10CopperCrackDefinition7

Note1.“A”cracks-crackinexternalfoil.

IPC-6012e-3-10

Figure3-11 SeparationsatExternalFoil

IPC-6012e-3-11

Note2.“B”cracks-crackdoesnotcompletelybreakplating.

Note3.“C”cracks-crackininternalfoil.

Note4.“D”cracks-completefracture.

Ndte5.“E”cracks-barrelcrackinplatingonly.

Note6.“F”cracks-cornercrackinplatingonly.

Note7:Copperplatingasshownmayincludemultipleplatinglayersorcapplating.

Note1.Conductivecoatings.

Note2.Electrolyticcopper.

Note3.Areaofacceptableseparationalongtheverticaledgeoftheexternalfoil.

Figure3-12PlatingFolds/Inclusions-MinimumMeasurementPoints

Note1.Minimumcopperplatemeasurementpoint.PlatingfoldsthatarenotenclosedandwheretheminimumcopperplatethicknessinTables3-4,3-5,or3-6ismetareacceptable.

Note2.Enclosedplatingfolds(inclusions)withdemarcationlinevisible.MeasureandacceptperNote1.

Note3.Enclosedplatingfoldwithnovisibledemarcationline.ThethicknessmeasurementA+BshallcomplywiththeminimumcopperplatethicknessinTables3-4,3-5,or3-6.

Note4.Minimumcopperplatemeasurementpointfornegativeetchback.

LaminateVoidsForClass2andClass3products,thereshallbenolaminatevoidsoutsideofanythermalzones(seeFigure3-13)inexcessof80pm[3,150pin].ForClass1products,voidsallowedoutsideofanythermalzone(seeFig-ure3-13)shallnotexceed150pm[5,906pin].Boundarylinevoidsthatoverlapintoathermalzoneshallnotbeinexcessof80pm[3,150pin]forClass2orClass3productsand150pm[5,906pin]forClass1products.Multiplevoidsbetweentwoadjacentplatedholesinthesameplaneshallnothaveacombinedlengthwhichexceedstheselimits.Voidsbetweenconductivepatternsthatarenotelectricallycommonineitherthehorizontalorverticaldirectionshallnotdecreasetheminimumdielectricspacing.

26

Market

Your

Business

Join

the

Leaders

in

IPC

USEIPC’SGLOBAL

reachandexclusivememberbenefitstoincreaseyourcompany’svisibility.

BuildyourbrandbyusingtheIPCmemberlogotohighlightyourcompany’sinvolvement,plusgetfreelinksfromIPC’sWebsitetoyourWebsite.

BelistedinIPC’sonlinemembershipdirectoryavailabletoallIPCmembers.

Putyourproducts,servicesandqualificationsinfrontofkeycustomerswithalistinginIPC’sProductsandServicesIndex(PCBandEMScompaniesonly).

ExhibitinIPC’sannualtradeshowandconference,IPCAPEXEXPO,plustheIPCMidwestConference&Exhibitionataspecialmemberprice.

GainvaluableexposurebysponsoringmarketresearchconferencesandManagementMeetingsatdiscountedrates.

Contain

Costs

TAKEADVANTAGEOFexclusivesavingsopportunitiesthatcaneasilyoffsetyourannualmembershipinvestment.

Getdiscountsofupto50percentonIPCstandards,publicationsandtrainingmaterials.

SavemoneyonsubscriptionpurchasesofIPCstandardsthroughIHS.Saveupto25percent.

Enjoydramaticdiscountsonregistrationfeesformeetings,technicalconferences,workshopsandtutorials.

BenefitfrompreferredpricingonexhibitspaceatIPCtradeshowsandevents.

WHATEVERSEGMENTOFtheindustryyouarein—PCBdesign,boardmanufacturing,electronicsmanufacturingservices(EMS),originalequipmentmanufacturer(OEM),industrysupplier,governmentagency,educationalinstitution—IPCmembershiphassomethingtooffervirtuallyeveryone

BenefitsofIPCMembership

atyoursite.PuttheresourcesoftheentireindustrybehindyourcompanybyjoiningIPCtoday!

Formorethan50years,companyleadershavelookedtoIPC–AssociationConnectingElectronicsIndustries?forthetools,informationandforumstheyneedtothriveintheever-changingelectronicinterconnectindustry.

Asamember-drivenorganizationandleadingsourceforindustrystandards,training,marketresearchandpublicpolicyadvocacy,IPCsupportsprogramstomeettheneedsoftheestimated$1.5trillion(U.S.dollars)globalelectronicsindustry.

Whateveryourroleintheindustry—asmallstart-upcompany,aneducationalorgovernmentinstitutionoraFortune?500firm—youcanjoinmorethan2,700companiesworldwidethatenjoyaccesstounparalleledopportunitiestoparticipateinandshapethedirectionofourcollectivefuture.

TolearnmoreaboutIPCmembershipandapplyonline,visit

.

--`,`,`,`,,`,,,,`,,,``,``,,,`,-`-`,,`,,`,`,,`---

February2009

Put

Membership

to

Work

IPC

for

YOU

Stay

Current

Shape

the

Industry

BEINFORMEDOFwhat’shappeningintheindustrynowandinthefuture…andwhatyouneedtodotoprepareandrespond.

GetFREEaccesstomembers-onlyonlineresources,includingasearchablearchiveoforiginalarticlesonthelatesttechnicalissuesandindustry/markettrends.

Accessmarketresearchstudiesandreportsandlearnaboutthelatesttrendsinmarketsandtechnologythrough