1、1,Digital Logic Design and ApplicationLecture #10,Combinational Logic Design Practices Documentation Standard and Circuit Timing,UESTC, Spring 2013,2,Chapter 6 Combinational Logic Design Practices,How to conceive a complex system? structured thinking Some useful combinational components,3,6.1 Docume

2、ntation Standard,A documentation package contain the following items: Specification: description of interface and function Block diagram: systems major function module and their basic interconnections Schematic diagram （P360 Figure 6-17） Timing diagram （P363 Figure 6-19） Structured logic device desc

3、ription Circuit description: explains how the circuit works internally,4,schematic diagram,5,1. Block Diagrams,A block diagram shows the inputs, outputs, functional modules, internal data paths, and important control signals of a system. P345 Figure 6-1,6,2. Gate Symbols,7,Equivalent Gate Symbols un

4、derthe Generalized Demorgans Theorem,inverter,buffer,AND NAND NOR OR,OR NOR NAND AND,8,3. Active Levels,active level active high and active low asserted: a signal is at its active level negated / deasserted: signal is not at its active level signal name Active levels for pins,Logic Functions are per

5、formed inside the symbolic outlines.,Indicate an Active-Low Pin,與門和或門的輸入為1才能確保其輸出,9,Example: active levels,Signal active state: switchoff, lamplight,Switch: 1off Lamp: 1light,Switch: 0off Lamp: 0light,F = A + B = ( A B ),AND: the output is asserted if and only if all its inputs are asserted.,Positiv

6、e Logic 1：High Level 0： Low Level,Active High,Active Low,10,Example: active levels,Active state: switchoff, lamplight,AND: the output is asserted if and only if all its inputs are asserted.,Inversion bubble active-low pin,Logic Functions are performed inside the symbolic outlines.,11,5. Bubble-to-Bu

7、bble Logic Design,P353 bubble-to-bubble logic design rules,12,7. Drawing Layout,flat schematic structure,13,Hierarchical schematic structure,14,timing diagram,Causality and Propagation Delay,6.2 Circuit Timing,15,Minimum and maximum delays,6.2 Circuit Timing,16,6.2 Circuit Timing,propagation delay,Timing analysis: worst-case delay,P366 Table 6-2,tpHL and tpLH may be different,17,Timing diagrams for “data” signals,must be stable,old,new,18,Some Useful Combinational Components,Decoder