1、課程：CPLD與FPGA設(shè)計及應(yīng)用實驗：基于VHDL語言的數(shù)字時鐘設(shè)計 學號：092030030姓名： 朱 峰 專業(yè)：信號與信息處理 學院：電子與信息學院2011年12月基于VHDL語言的數(shù)字時鐘設(shè)計一：主要功能1：具有時、分、秒計數(shù)顯示功能，以24小時循環(huán)計時。2：具有日期和星期顯示功能。3：具有秒表功能4：具有調(diào)節(jié)日期，星期，小時，分鐘，清零的功能。5：具有定時和鬧鈴的功能。二：結(jié)構(gòu)框圖控制單元使能信號數(shù)字時鐘CLK時鐘信號報警（鬧鈴）信號復(fù)位信號輸出信號LED顯示揚聲器三：RTL圖四：功能實現(xiàn) 4.1分頻模塊設(shè)計 本設(shè)計使用的輸入時鐘信號為50Mhz，經(jīng)過分頻產(chǎn)生兩路時鐘信號，其中一路為

2、微秒計數(shù)時鐘信號，一路為動態(tài)掃描時鐘信號。同時模塊有一輸入控制信號，其功能是停止微秒計數(shù)時鐘信號，以實現(xiàn)定時的功能。輸入：clk_in 為50Mhz，setstop為微秒計數(shù)時能信號輸出：clk_out1為1/60hz clk_out2為1khz源代碼如下：library ieee;use ieee.std_logic_1164.all;entity div is port(clk_in,setstop: in std_logic; clk_out1,clk_out2: out std_logic);end entity div;architecture fun of div isconsta

3、nt a:integer:=8333333;constant b:integer:=49999;signal c:integer range 0 to a;signal d:integer range 0 to b;beginprocess(clk_in,setstop) begin if(clk_in 'event and clk_in='1') then if( c+7500000)<a and setstop='1') then c<=c+1;clk_out1<='1' else c<=0;clk_out1&

4、lt;='0' end if; end if;end process;process(clk_in) begin if(clk_in 'event and clk_in='1') then if d<=b then d<=d+1; clk_out2<='1' else d<=0;clk_out2<='0' end if; end if;end process;end fun;4.2計時模塊設(shè)計 微秒計時模塊 計數(shù)器的第一個模塊為微秒計時模塊，其實質(zhì)為一個六十進制計數(shù)器。輸入：clk為1/60h

5、z，reset為清零復(fù)位鍵輸出：ensecond為秒模塊的進位信號 Daout為微妙輸出顯示信號源代碼如下：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity msecond isport(clk,reset:in std_logic; ensecond:out std_logic; daout:out std_logic_vector(6 downto 0);end entity msecond;architecture fun of msecond is signal count:s

6、td_logic_vector(6 downto 0); signal enmin_1:std_logic;beginprocess(clk,reset)begin if(reset='0')then count<="0000000" elsif(clk 'event and clk='1')then if(count(3 downto 0)="1001")then if(count<16#60#)then if(count="1011001")then enmin_1<=&#

7、39;1'count<="0000000" else count<=count+7; end if; else count<="0000000" end if; elsif(count<16#60#)then count<=count+1 ; enmin_1<='0' ; else count<="0000000" end if; end if;end process; daout<=count; ensecond<=enmin_1 ;end fun; 秒計

8、時模塊 計數(shù)器的第二個模塊為秒計時模塊，其實質(zhì)為一個六十進制計數(shù)器。輸入：clk為秒進位信號，reset為清零復(fù)位鍵，setmin為調(diào)分信號，setclk為消抖時鐘輸出：enmin為分模塊的進位信號 daout為秒輸出顯示信號源代碼如下：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity second isport(clk,setclk,reset,setmin:in std_logic; enmin:out std_logic; daout:out std_logic_vector(6

9、 downto 0);end entity second;architecture fun of second is signal count:std_logic_vector(6 downto 0); signal enmin_1,enmin_2:std_logic;beginprocess(clk,reset,setmin)begin if(reset='0')then count<="0000000" elsif(clk 'event and clk='1')then if(count(3 downto 0)="

10、1001")then if(count<16#60#)then if(count="1011001")then enmin_1<='1'count<="0000000" else count<=count+7; end if; else count<="0000000" end if; elsif(count<16#60#)then count<=count+1 ; enmin_1<='0' ; else count<="0000

11、000" end if; end if;end process;process(setclk,setmin)begin if(setclk 'event and setclk='1') then enmin_2<=not setmin ; end if; end process; daout<=count; enmin<=(enmin_1 or enmin_2);end fun;4.2.3 分計時模塊 計數(shù)器的第三個模塊為秒計時模塊，其實質(zhì)為一個六十進制計數(shù)器。輸入：clk為分進位信號，reset為清零復(fù)位鍵，sethour為調(diào)時信號，set

12、clk為消抖時鐘輸出：enhour為小時模塊的進位信號 daout為分輸出顯示信號源代碼如下：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity minute isport( clk,setclk,reset,sethour:in std_logic; enhour:out std_logic; daout:out std_logic_vector(6 downto 0);end entity minute;architecture fun of minute is signal cou

13、nt:std_logic_vector(6 downto 0); signal enhour_1,enhour_2:std_logic;beginprocess(clk,reset)begin if(reset='0')then count<="0000000" elsif(clk 'event and clk='1')then if(count(3 downto 0)="1001")then if(count<16#60#)then if(count="1011001")then

14、enhour_1<='1' count<="0000000" else count<=count+7; end if; else count<="0000000" end if; elsif(count<16#60#)then count<=count+1; enhour_1<='0' ; else count<="0000000" end if; end if; end process;process(setclk,sethour)begin if(se

15、tclk 'event and setclk='1') then enhour_2<=not sethour ; end if; end process; daout<=count; enhour<=(enhour_1 or enhour_2);end fun;4.2.4小時計時模塊 計數(shù)器的第四個模塊為小時計時模塊，其實質(zhì)為一個二十四進制計數(shù)器。輸入：clk為分進位信號，reset為清零復(fù)位鍵，setweek為調(diào)小時信號，setclk為消抖時鐘輸出：enweek為日期模塊的進位信號 daout為小時輸出顯示信號源代碼如下：library ieee;u

16、se ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity hour isport( clk,setclk,reset,setweek:in std_logic; enweek:out std_logic; daout:out std_logic_vector(6 downto 0);end entity hour;architecture fun of hour is signal count:std_logic_vector(6 downto 0); signal enweek_1,enweek_2:std_logic

17、;begin process(clk,reset)begin if(reset='0')then count<="0000000" elsif(clk 'event and clk='1')then if(count(3 downto 0)="1001") and (count<16#23# )then count<=count+7; elsif (count="0100011")then enweek_1<='1'count<="0000

18、000" elsif(count<16#23#)then count<=count+1; enweek_1<='0' else count<="0000000" end if; end if;end process;process(setclk,setweek)begin if(setclk 'event and setclk='1') then enweek_2<=not setweek; end if; end process; daout<=count; enweek<=(en

19、week_1 or enweek_2) ;end fun;4.3日期和星期模塊設(shè)計 星期顯示模塊 星期顯示模塊其實質(zhì)為一個七進制計數(shù)器。輸入：clk為日期進位信號，reset為清零復(fù)位鍵輸出：weeoutk為星期輸出顯示信號源代碼如下：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity weeker is port(clk:in std_logic; reset:in std_logic; weekout:out std_logic_vector(3 downto 0);end enti

20、ty weeker;architecture fun of weeker issignal count:std_logic_vector(3 downto 0);beginprocess(clk,reset) begin if(reset='0')then count<="0001" elsif(clk 'event and clk='1')then if (count<16#7#) then count<=count+1; else count<="0001" end if; end if

21、; end process; weekout<=count; end fun; 日期顯示模塊 日期顯示模塊其實質(zhì)為一個十二選一選擇器。輸入：clk為日期進位信號，reset為清零復(fù)位鍵輸出：monthout 為月輸出顯示信號 Dateout為日輸出顯示信號源代碼如下：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity date is port(clk:in std_logic; reset:in std_logic; monthout:out std_logic_vector(4

22、downto 0); dateout:out std_logic_vector(5 downto 0);end entity date;architecture fun of date issignal dount:std_logic_vector(4 downto 0);signal count:std_logic_vector(5 downto 0);beginprocess(clk,reset) begin if(reset='0')then count<="000001"dount<="00001" elsif(clk

23、 'event and clk='1' and dount="00001" )then if(count(3 downto 0)="1001") and (count<16#31# )then count<=count+7; elsif (count<16#31#) then count<=count+1; else count<="000001"dount<=dount+1;end if; elsif(clk 'event and clk='1' a

24、nd dount="00010" )then if(count(3 downto 0)="1001") and (count<16#29# )then count<=count+7; elsif (count<16#29#) then count<=count+1; else count<="000001"dount<=dount+1;end if; elsif(clk 'event and clk='1' and dount="00011" )then

25、if(count(3 downto 0)="1001") and (count<16#31# )then count<=count+7; elsif (count<16#31#) then count<=count+1; else count<="000001"dount<=dount+1;end if; elsif(clk 'event and clk='1' and dount="00100" )thenif(count(3 downto 0)="1001&qu

26、ot;) and (count<16#30# )then count<=count+7; elsif (count<16#30#) then count<=count+1; else count<="000001"dount<=dount+1; end if; elsif(clk 'event and clk='1' and dount="00101" )then if(count(3 downto 0)="1001") and (count<16#31# )then

27、count<=count+7; elsif (count<16#31#) then count<=count+1; else count<="000001"dount<=dount+1; end if; elsif(clk 'event and clk='1' and dount="00110" )then if(count(3 downto 0)="1001") and (count<16#30# )then count<=count+7; elsif (count&

28、lt;16#30#) then count<=count+1; else count<="000001"dount<=dount+1;end if; elsif(clk 'event and clk='1' and dount="00111" )then if(count(3 downto 0)="1001") and (count<16#31# )then count<=count+7; elsif (count<16#31#) then count<=count+1

29、; else count<="000001"dount<=dount+1;end if; elsif(clk 'event and clk='1' and dount="01000" )then if(count(3 downto 0)="1001") and (count<16#31# )then count<=count+7; elsif (count<16#31#) then count<=count+1; else count<="000001&quo

30、t;dount<=dount+1;end if; elsif(clk 'event and clk='1' and dount="01001" )then if(count(3 downto 0)="1001") and (count<16#30# )then count<=count+7; elsif (count<16#30#) then count<=count+1; else count<="000001"dount<=dount+1; end if; elsi

31、f(clk 'event and clk='1' and dount="01010" )then if(count(3 downto 0)="1001") and (count<16#31# )then count<=count+7; elsif (count<16#31#) then count<=count+1; else count<="000001"dount<=dount+1;end if; elsif(clk 'event and clk='1&#

32、39; and dount="01011" )then if(count(3 downto 0)="1001") and (count<16#30# )then count<=count+7; elsif (count<16#30#) then count<=count+1; else count<="000001"dount<=dount+1; end if; elsif(clk 'event and clk='1' and dount="01100"

33、)then if(count(3 downto 0)="1001") and (count<16#31# )then count<=count+7; elsif (count<16#31#) then count<=count+1; else count<="000001"dount<=dount+1;end if;end if; end process; monthout<=dount; dateout<=count; end fun;4.4掃描顯示模塊設(shè)計 該模塊的作用是將時鐘產(chǎn)生的微秒、秒、分、小時、

34、星期和日期信號以掃描的形式顯示輸出。其中一控制信號實現(xiàn)數(shù)碼管的復(fù)用，控制顯示微秒、秒、分、小時或星期、日期。輸入：clk1為掃描時鐘，reset為清零復(fù)位鍵，ms、sec、min、hour、month、date、week分別為微秒、秒、分、小時、月、日、星期顯示信號，showweek為控制信號輸出：dp為數(shù)碼管小數(shù)點顯示信號 led為七段數(shù)碼管顯示信號 sel為位選信號源代碼如下：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity

35、 seltime isport( clk1,reset,showweek:in std_logic; ms,sec,min,hour:in std_logic_vector(6 downto 0); month:in std_logic_vector(4 downto 0); date:in std_logic_vector(5 downto 0); week:in std_logic_vector(3 downto 0); dp:out std_logic; led:out std_logic_vector(6 downto 0); sel:out std_logic_vector(7 do

36、wnto 0);end entity seltime ;architecture fun of seltime issignal count:std_logic_vector(3 downto 0);signal daout:std_logic_vector(3 downto 0);signal d:std_logic_vector(4 downto 0);beginp1 : process(clk1,reset)begin if(reset='0')then count<="0000" elsif(clk1'event and clk1=&#

37、39;1') then if(count>"1101")then count<="0000" d<=count&showweek ; else count<=count+1; d<=count&showweek ; end if; end if;end process p1;p2: process(d) begin case d iswhen"00011" =>daout<=ms(3 downto 0);sel<="01111111"dp<

38、;='1' when"00101"=>daout(3)<='0'daout(2 downto 0)<=ms(6downto4);sel<="10111111"dp<='1' when"00111" =>daout<=sec(3 downto 0);sel<="11111110"dp<='0' when"01001"=>daout(3)<='0'daou

39、t(2downto0)<=sec(6 downto 4);sel<="11111101"dp<='1' when"01011" =>daout<=min(3 downto 0);sel<="11111011"dp<='0' when"01101"=>daout(3)<='0'daout(2downto0)<=min(6downto 4);sel<="11110111"dp<=&

40、#39;1' when"01111" =>daout<=hour(3 downto 0);sel<="11101111"dp<='0'when"10001"=>daout(3downto2)<="00"daout(1downto0)<=hour(5downto4);sel<="11011111"dp<='1'when"10010" =>daout<=week;sel<

41、;="01111111"dp<='1'when"10100" =>daout<=date(3 downto 0);sel<="11111110"dp<='1'when"10110"=>daout(3downto2)<="00"daout(1downto0)<=date(5downto4);sel<="11111101"dp<='1'when"11000&quo

42、t; =>daout<=month(3 downto 0);sel<="11111011"dp<='1'when"11010" =>daout(3 downto 1)<="000"daout(0)<=month(4);sel<="11110111"dp<='1' when others=>sel<="11111111" end case;end process p2;p3: process(daou

43、t) begin case daout is when"0000"=>led<="0000001"when"0001"=>led<="1001111"when"0010"=>led<="0010010"when"0011"=>led<="0000110" when"0100"=>led<="1001100"when"0101&q

44、uot;=>led<="0100100" when"0110"=>led<="0100000"when"0111"=>led<="0001111"when"1000"=>led<="0000000"when"1001"=>led<="0000100" when others=>null;end case;end process p3;end fun;4

45、.5 整點報時模塊設(shè)計 該模塊的作用是當時鐘計數(shù)到整點時蜂鳴器報警，以實現(xiàn)整點報時功能。輸入：clk計數(shù)時鐘信號，speaksec秒輸出信號，speakmin分輸出信號輸出：報警信號源代碼如下：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity speaker is port(clk:in std_logic; speaksec:in std_logic_vector(6 downto 0); speakmin:in std_logic_vector(6 downto 0); speak

46、:out std_logic);end entity speaker;architecture fun of speaker isbeginprocess(clk,speakmin)begin if(clk 'event and clk='1')then if(speakmin="0000000" and speaksec="0000000")then speak<='1'else speak<='0'end if; end if;end process;end fun;五：附錄頂層文件

47、源代碼：library ieee;use ieee.std_logic_1164.all;entity clock_top isport(clk_in,reset,setmin,sethour,setweek,setstop,showweek:in std_logic; dp:out std_logic; sel:out std_logic_vector(7 downto 0); led:out std_logic_vector(6 downto 0); speak: out std_logic);end clock_top;architecture a of clock_top isCOMP

48、ONENT div PORT(clk_in,setstop: in std_logic; clk_out1,clk_out2: out STD_LOGIC);END COMPONENT;COMPONENT msecond PORT(clk,reset: in std_logic; daout:out std_logic_vector(6 downto 0); ensecond:out std_logic);END COMPONENT;COMPONENT second PORT(clk,setclk,reset,setmin: in std_logic; daout:out std_logic_

49、vector(6 downto 0); enmin:OUT STD_LOGIC);END COMPONENT;COMPONENT minute PORT(clk,setclk,reset,sethour:in std_logic; enhour:out std_logic; daout:out std_logic_vector(6 downto 0);END COMPONENT;COMPONENT hour PORT(clk,setclk,reset,setweek:in std_logic; enweek:out std_logic; daout:out std_logic_vector(6

50、 downto 0);END COMPONENT;COMPONENT weeker PORT(clk,reset:in std_logic; weekout:out std_logic_vector(3 downto 0);END COMPONENT; COMPONENT date PORT(clk,reset:in std_logic; monthout:out std_logic_vector(4 downto 0); dateout:out std_logic_vector(5 downto 0);END COMPONENT; COMPONENT seltime port(clk1,re

51、set,showweek:in std_logic; ms,sec,min,hour:in std_logic_vector(6 downto 0); week:in std_logic_vector(3 downto 0); month:in std_logic_vector(4 downto 0); date:in std_logic_vector(5 downto 0); dp:out std_logic; sel:out std_logic_vector(7 downto 0); led:out std_logic_vector(6 downto 0);END COMPONENT;CO

52、MPONENT speaker PORT(clk:in std_logic; speaksec:in std_logic_vector(6 downto 0); speakmin:in std_logic_vector(6 downto 0); speak:out std_logic);END COMPONENT;signal da0out,dalout,dallout,dalllout:std_logic_vector(6 downto 0);signal dallllout:std_logic_vector(3 downto 0);signal month0out:std_logic_ve

53、ctor(4 downto 0);signal date0out:std_logic_vector(5 downto 0);signal ensecond_re,enmin_re,enhour_re,enweek_re,dp_re,clk00,clk01:std_logic;beginu1:div port map (clk_in=>clk_in, setstop=>setstop, clk_out1=>clk00, clk_out2=>clk01); u2:msecond port map (clk=>clk00, reset=>reset, enseco

54、nd=>ensecond_re, daout=>da0out);u3:second port map (clk=>ensecond_re, setclk=>clk01, reset=>reset, setmin=>setmin, enmin=>enmin_re, daout=>dalout);u4:minute port map (clk=>enmin_re, setclk=>clk01, reset=>reset, sethour=>sethour, enhour=>enhour_re, daout=>dal

55、lout);u5:hour port map (clk=>enhour_re, setclk=>clk01, reset=>reset, setweek=>setweek, enweek=>enweek_re, daout=>dalllout);u6:weeker port map (clk=>enweek_re, reset=>reset, weekout=>dallllout);u7:date port map (clk=>enweek_re, reset=>reset, monthout=>month0out, dateout=>date0out);u8:seltime port map(clk1=&g