1、組合邏輯組合邏輯 電路電路1a2ana1y2ymy組合邏輯電路的框圖組合邏輯電路的框圖)(AFY ）aa(afy)aa(afy)aa(afynmmnn2121222111如果信號(hào)燈如果信號(hào)燈出現(xiàn)故障，出現(xiàn)故障，Z為為1RAGZRAGRAGGRAAGRGARZAGRGRAGARZ012345670123456701234567012345672IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIY753107632176542IIIIYIIIIYIIIIY45675676772IIIIIIIIIIY45672IIIIYBABAA低電平)()()(SIIIIIIIIIIYSIIIIII

2、IIYSIIIIY6421643567054234567145672)(45672IIIIY選通信號(hào))(SIIIIY45672)()()(SIIIIIIIISSIIIIIIIIYSIIIIIIIIYEXS012345670123456701234567為0時(shí)，電路工作無(wú)編碼輸入為0時(shí)，電路工作有編碼輸入76543210IIIIIIIIS012YYYEXSYYEXSYY15A0EXY815AA19II9I0IEXY70127201221012100120mAAAYmAAAYmAAAYmAAAY.用二極管與門(mén)陣列組成的3線8線譯碼器低電平輸出附加控制端123SSSS )(iimSY 32SS 01

3、234567YYYYYYYYiimZ D3=1D3=0)(90imYiiimYABCCBBCAZCABBAZCBABCZCABBCAACZ4321),(),(),(),(742053273165434321mABCCBBCAZmCABBAZmCBABCZmCABBCAACZ)(),()(),()(),()(),(74204532373126543174205327316543mmmmmZmmmmZmmmmZmmmmmZ)()()()()()()(0121230112023012012012012012230120121302130123AAAAAAYAAAAAAAYAAAYAAAAAAAAAY

4、AAAAAYAAAAAAAAYAAAAAAAAYgfedcbaLT當(dāng) 時(shí)，Ya Yg全部置為10LTRBI當(dāng) 時(shí)， 時(shí)，則滅燈0RBI00000123AAAARBOBI0BI00123AAAA0RBIRBO0RBORBIRBORBORBIRBORBI)()()()(01301201101011AADAADAADAADSY1S70126012501240123012201210120012DAAADAAADAAADAAADAAADAAADAAADAAAY)()()()()()()()(位地址輸入端作為第利用3S)()()()(0130120110101AADAADAADAADY)()()()(A

5、GAGRGARGARRAGRAGGRAAGRGARZ1)()()()(01301201101011AADAADAADAADSYABCOBAS)()(CIACIBBACOABCICIABCIBACIBASiiiiiiiiiiiiCIBABACOCIBASCOCI)()()()()(1)()()()()()()()()()()()(:)()()()()()()()(:)()()()(:0000011112222220000011112222222222000001111120000011110111110000011011101000000000002100CIBABABABABACIBASCIB

6、ABABABABABACIBABACOCIBABABABACOCIiCIBABABABACOBABACOCIBABABACOBASCOCIiCIBABACOCIBASCIi00110123 DCBAYYYY？D2D1D0)()()()(),(,),(,),(BAYBABABAYBABABAABYABBABABABABA10110101或同為則則)()()()()()()()()()()()()()()()(BABABABABAYYYBABABABAYBABABABABABABABABABAYBBBBAAAA001122330011223311223322333301230123和比較為附加端，用于擴(kuò)展和)()()(,BABABAIII輸出允許信號(hào)來(lái)自低位的比較結(jié)果來(lái)自低位的比較結(jié)果BAIIIBA