會計學1DisplayPort和eDP物理層兼容性測試中必須考慮的因素TopicsDisplayPort

TechnologyeDP

andMyDP

CapabilitiesTesting

Considerations第1頁/共49頁Something

Good

is

Happening…MyDPStandardDisplayPortComputingeDPEmbeddedSystemsConsumer

ElectronicsPortablesVESA:

200

members

strong!第2頁/共49頁DisplayPort

Technology

RolloutsConfidentialityLabelMay

10,20134MyDPDP1.2iDP

1.0DP1.0DP1.1eDP

1.01.21.31.41/2013DP1.3Today1.0CTS

ReleasedSpecification

Released4/2013Standard

DP5/20127/20135/2012

12/2012第3頁/共49頁Quick

SummaryStandardDisplayPorteDPMyDPCapabilitiesNoteworthyFeaturesCompetingTechnologyP1,2,or4lanesFour

Settings

forLvl

and

Pre-emphSSC3

bit

ratesHDMIDVI?VGA?Integrable

in

lowgeometry

silicon.Dominating

inPCs

now.1,2,or4lanesMulti-LevelPre-emphSSCMulti

bit

ratesLVDSMIPILow

Power

rivalsMIPI.

High

data

ratessupported

now.Attributes

similar

toDP1laneFour

LevelsPre-emphasisSSC3

bit

ratesMHL1080p/60

24

bit

colorachieved.

Manyconnection

models.Attributes

same

as

D第4頁/共49頁Why

Successful?200

member

companies

participatingOriginal

DP

foundational

principles

serving

DP

extensionsConsumer

focus

in

handling

Legacy

designsInteroperability

Program/Self

testing/Compliance

testingKnowledgeable

and

Aggressive

leadersCraigWileyParade

TechnologiesAlan

KobayashiST

Micro第5頁/共49頁Key

Features

of

DisplayPortHot

Plug

DetectTransmitterAUXReceiver

(Sink)AUX

ChannelVery

robust

channelSetup

Link/Maintain

LinkTest

AssistanceuPacketBasedNot

based

on

Raster

timingsFixed

bit

ratesPhysical

Layer

FeaturesMultiple

Bit

ratesMultiple

LevelsMultiple

Pre

Emphasis

SettingsSpread

Spectrum

ClockingActive

VideoBlanking

Area第6頁/共49頁DisplayPort

LinkThe

AUX

Channel

enables

Link

setup

and

maintenance

as

well

ascontrol

for

testing.TxDriverLogicDecodeMain

LinkAUXHot

Plug

DetectImagebufferEDIDDPCDSinkLogicBitRecoveryLockImageFramebufferDisplayErrAUX

CHCom第7頁/共49頁AUX

Channel

Implementation

Manchester

II

Signaling第8頁/共49頁MyDP: Portable

TVPortable

Get

apic

ofU-Tube

or

NetflicksIn

the

Future:Wireless

fromyour

portableToday:MyDP

Connectivity第9頁/共49頁My

EntertainmentSystemYour

EntertainmentSystem第10頁/共49頁Transmission

Requirements4k

x

2k

?No

Way!Not

Yet

AnywayUsing

HDMI

transmission

as

a

benchmark…Display

TechnologiesAvailable:DisplayPort:

Maximum

Lane

Rate--5.4GbsHDMI:

Maximum

Lane

Rate3.4GbsTiming1080i/720p1080p/8bit1080p/10bitLane

Bit

Rate750Mbs1.50Gbs1.87GbsPixel

Rate75MPs150MPs187MPsComposite

Bit

Rate2.23Gbs4.46Gbs5.57Gbs第11頁/共49頁Let’s

Look

Closer…For

both

MHL

and

MyDP

the

uUSB

connector

isthe

defactoconnector,butitis

notfind

itmentioned

in

eitherstandard!D-

and

D+

isthe

differential

data

laneID:USB

mode

detectConclusion:

There

is

only

one

data

lanethrough

whichthe

composite

data

rate

must

be

conveyed. Sothe

composite

bitrate

rate

isthe

metric.5

Pins第12頁/共49頁Getting

down

to

One

data

lane…5

Pins1

datalane4

datalanesAUX+/-,

HPDConfig1/21lowMyDP

speedlineDisplayPort20

PinsPower,GroundPower,Ground第13頁/共49頁HDMIMyDPuUSB HDMISpec

Released:

1.0Compliance

Testing

starting:

June

2013Maximum

Data

Rate:

5.4Gbs

to

support

1080p/60HzuUSBVGA第14頁/共49頁MyDPOne

could

say

that

MyDP

is

not

very

new!It

is

just

one

lane

DisplayPort!There

are

other

changes

to

get

to

5

pin

interface,

butnothing

changes

in

the

high

speed

signaling.Subsequent

slides

will

be

paired;

the

first

to

show

thestandard

DisplayPort

attributes

and

the

next

those

for

MyDP.第15頁/共49頁DisplayPort

TechnologyHot

Plug

Detect(Interrupt

Request)

1

to

4

unidirectional

high

speed

lanes–

Fixed

data

rate

independent

of

display

raster

(refresh)

Auxiliary

channel

for

link

communication

and

auxiliary

data

flowLink

Setup

and

Maintenance

(1Mb/s

-

Manchester

II

)USB

2.0

Transport

(Fast

AUX

-540Mb/s

-

standard

8b/10b)

Auto

detect

of

cable

plug/unplugSource

DeviceSink

DeviceDisplayPortTransmitterDisplayPortReceiverMain

Link(Isochronous

streams)AUX

ChLink/Device

ManagementFAUX:USB2.0

transport第16頁/共49頁MyDP

Technology

1

to

4

unidirectional

high

speed

lanes–

Fixed

data

rate

independent

of

display

raster

(refresh)

Auxiliary

channel

for

link

communication

and

auxiliary

data

flowLink

Setup

and

Maintenance

(1Mb/s

-

Manchester

II

)USB

2.0

Transport

(Fast

AUX

-540Mb/s

-

standard

8b/10b)

Auto

detect

of

cable

plug/unplugSource

DeviceSink

DeviceDisplayPortTransmitterDisplayPortReceiverMain

Link(Isochronous

streams)AUX

ChLink/Device

ManagementHot

Plug

Detect(Interrupt

Request)FAUX:USB2.0

transport

1

unidirectional

high

speed

lane–

Fixed

data

rate

independent

of

display

raster

(refresh)

Auxiliary

channel

for

link

communication

and

auxiliary

data

flowLink

Setup

and

Maintenance

(1Mb/s

-

Manchester

II

)Single

Ended

Polling

detect

of

cable

plug/unplugSingle

Ended第17頁/共49頁DP

Technology:

SpecificationsSilicon

structures:Structure

leveraged

from

PCI

ExpressImplementable

on

sub

65nm

processTermination

Voltage

must

be

<2volts

(internal

to

IC)ReceiverPLL

BW=10MHz

effective.Jitter

tolerance

curve

specified.Data

Rate1.62Gbs

(RBR)2.7Gbs (HBR) [units

supporting

HBR

must

support

RBR]5.4Gbs (HBR2)

[units

supporting

HBR2

must

support

HBR]第18頁/共49頁MyDP

Technology:

SpecificationsSilicon

structures:Structure

leveraged

from

PCI

ExpressImplementable

on

sub

65nm

processTermination

Voltage

must

be

<2volts

(internal

to

IC)ReceiverPLL

BW=10MHz

effective.Jitter

tolerance

curve

specified.Data

Rate1.62Gbs

(RBR)2.7Gbs5.4Gbs(HBR)(HBR2)第19頁/共49頁DP

Technology:

Main

Link

LanesLanesEach

lane

is

Differential,

100Ω.1,

2,

4

lane

models

for

video

data

transport. 4

lane

model

capable

mustsupport

1

&

2

lane

models.Lanes

are

uni-directional.ANSII

standard

8b/10b.2

lane

model

must

support

1

lane

model.Each

lane

has

separate

clock

recovery

from

its

data. No

Explicit

Clock.Single

ended

lines

of

each

lane

are

source

and

sink

terminated

andbiased. No

external

pull-up

is

needed

for

test

equipment.第20頁/共49頁MyDP

Technology:

Main

Link

LaneLanesEach

lane

is

Differential,

100Ω.1

lane

for

video

data

transport.

Lane

is

uni-directional.ANSII

standard

8b/10b.Clock

recovery

from

the

data.Single

ended

lines

of

each

lane

are

source

and

sink

terminated

andbiased. No

external

pull-up

is

needed

for

test

equipment.第21頁/共49頁DP

Technology:

Signal

AttributesFour

swing

settings:Setting

0:

400mV

nominalSetting

1:

600

mV

nominalSetting

2:

800

mV

nominalSetting

3:

1200

mV

nominal

(optional)Four

Pre-Emphasis settingsSetting

0:

0

dB

nominalSetting

1:

3.5

dB

nominalSetting

2:

6

dB

nominalSetting

3:

9.5

dB

nominal

(optional)Compliance

Test

Specification

em-phasizes monotonicity

not

accuracyNo

combination

of

voltage

and

pre-emphasis

can

exceed

1200mVolts

p-pSpread

Spectrum

Clocking(30-33KHz

spreading

frequency,downspread)第22頁/共49頁DP

Technology:

AUX

Channel,

DPCDDesignated

Control

Link

lane

called

‘the

AUX

Channel’

specified.Operates

at

1Mbs

and

is

used

in

Link

Training

and

Link

Management

andis

Bidirectional

Half

Duplex.The

Transmitter

is

the

master.Receiver

gains

attention

by

pulling

down

on

the

Hot

Plug

Detect

line.Manchester

II

coding(shown

subsequently)AUX

ControlHot

Plug

DetectSinkAUX+AUX-TransmitterReceiver

(Sink)TxDriverLogicDecodeMain

LinkAUXHot

Plug

DetectImagebufferEDIDDPCDLogicBitRecoveryLockImageFramebufferDisplayErrAUX

CHCom第23頁/共49頁MyDP:

AUX

Channel,

DPCDDesignated

Control

Link

lane

called

‘the

AUX

Channel’

specified.Operates

at

1Mbs

and

is

used

in

Link

Training

and

Link

Management

andis

Bidirectional

Half

Duplex.The

Transmitter

is

the

master.Receiver

identified

by

polling. Link

serviced

by

occasional

DPCD

reads.Manchester

II

coding(shown

next

page)AUX

ControlTransmitterReceiver

(Sink)AUX+TxDriverLogicDecodeMain

LinkAUXImagebufferEDIDDPCDLogicBitRecoveryLockImageFramebufferDisplayErrAUX

CHCom第24頁/共49頁DP

AUX

Channel

Implementation

Manchester

II

Signaling第25頁/共49頁MyDP

AUX

Channel

Implementation

Manchester

II

Signaling,

Single

Ended第26頁/共49頁MyDP

connection

requirements.620kΩ第27頁/共49頁Testing

MyDPGndAUX-HPDD-D+PwrMyDP

TransmittersAUX-HPDPower

ChargingWaveform

ParametricsVideo/Audio

Protocol

ValidationMyDP

ReceiversDisplayPort!Power

ChargingVideo/Audio

Protocol

ResponseReceiver

Sensitivity/Jitter

Tolerance(usingtest

mode

BER

counting)第28頁/共49頁Test

FixturesThese

arethe

MyDP

fixturesfrom

Wilder

Technologies.

.第29頁/共49頁MyDP

Fixture

SchematicConfidentialityLabelMay

10,201331From

Wilder:第30頁/共49頁MyDP

Source

TestingConfidentialityLabelMay

10,201332MYDPDeviceto

TestMyDPTPAOscilloscopeDisplayPort

Compliancetest

softwareThetest

suitefor

standard

DP

appliesfor

MyDPAUX

ChTPAAUX

Channelcontroller第31頁/共49頁Preparing

for

TestControl

of

yourMyDP

DeviceAgilentDisplayPortTest

ApplicationSetup

your

deviceMyDPMain

Link

Phy

TestsSingle

ended

AUX

Tests第32頁/共49頁PHY

Source

TestsEye

DiagramNon

Pre-Emph

LevelPre-Emphasis

LevelIntra

Pair

SkewEmp+-ConnectorTP1ChannelConnectorEQ+-TP2TP3TP4TxpTxnRxnRxpTxRxMyDP

source

testingis

at

TP2

onlyJitter:

Non

ISI,Total

Jitter,HBR2

RJ/DJ/TJMain

Link

FrequencyAUX

EyeAUX

Sensitivity第33頁/共49頁MyDP

Sink

TestingMyDP

‘Sink’

Calibration

and

TestCalibrationTest

EquipmentTestDongleuUSBPLUGSignalConditioningVGADVIHDMIDPuUSB

PluguUSBReceptacleThetest

suitefor

standard

DP

appliesfor

MyDP.Specs

are

different第34頁/共49頁Rec+ISI)N4903B

JBERTSink

Test

Jitter

Components

(RJ+DJRJDJISIRxChipTxLoop

BackRJR+JDR+JJD+JISIError

DetectionPage

36Sink

Device第35頁/共49頁Summary

of

MyDPMyDP

is

merely

1lane

DP

so

no

modifications

on

the

main

link

or

protocol.Only

significant

changeis

that

the

AUXlaneis

Single

ended,

and

therefore,theAUX

sensitivityis

halved.MyDP

can

do

1080p/60

with

24

bits

of

color.Same

Connector,uUSB

as

MHL.

Nothing

else

in

common!第36頁/共49頁eDP1.4Huge

changes

from

eDP

1.3AttributeeDP

1.3eDP1.4Levels4

(std

DP)6

(200mv-450mV)Arbitrary

allowedBit

Rates3

(std

DP)7

(1.45

to

5.4Gbs)Arbitrary

allowedPre-Emphasis4

(std

DP)ArbitraryPanel

Self

RefreshWhole

frame

onlyPartial

FrameenabledCompressionNoYesMulti-touchNoYesBackLight

controlYesYes

Regional

controlaswell第37頁/共49頁AUX

Channel

ExtendedTxDriverLogicDecodeMain

LinkAUXImagebufferAPRLEDIDDPCDSinkLogicBitRecoveryLockImageFramebufferPSRM-TouchBackLightDataCompDisplayErrAUX

CHComHot

PlugDetect第38頁/共49頁Levels/PreEmphasis/BitRates第39頁/共49頁Reference

Equalizers

(for

measurements

only)第40頁/共49頁Test

PointsAvailableeDP

Test

Point.Test

Fixture&Test

ModelTest

ataModified

TP2.第41頁/共49頁Testing

eDPLots

of

bit

rates

and

levels

and

arbitrary

settings

are

allowed.TestPoint

is

TP3,

the

cable

is

considered

part

of

the

sourceA

Test

guideline

is

being

created

now. Mike

Hamann

of

Intelis

leading

this

effort.VESA?

eDP1.4

PHY

Compliance

Test

Guideline,

Version

1.0OPEN

ISSUES:HBR2

Pattern

CP2520,Data

Rate

Measurement

(SSC),TX

AUX

Channel

Eye

DerivationRX AUX

Over-Sampling

Assumptions第42頁/共49頁Testing

eDPEmp+-ConnectorTP1ChannelConnectorEQ+-TP2TP4TxpTxnRxnRxpTxRxTP3eDP

sourcetest