實(shí)驗(yàn)?zāi)? 理解計(jì)算機(jī)5大組成部分的協(xié)調(diào)工作原理，理解程序自動(dòng)執(zhí)行的原掌握I/O端口的設(shè)計(jì)方法，理解I/OI/O VerilogHDLquartus20MIPS指令的單周期CPU設(shè)計(jì)。采用I/O統(tǒng)一編址方式，即將輸入輸出的I/O地址空間，作為數(shù)據(jù)存取CPU與外部設(shè)備的輸入輸出端口設(shè)計(jì)。實(shí)驗(yàn)中可采利用設(shè)計(jì)的I/O端口，通過lw指令，輸入DE2實(shí)驗(yàn)板上的按鍵等輸入設(shè)備信息。即將外部設(shè)備狀態(tài)，讀到CPU內(nèi)部寄存器。利用設(shè)計(jì)的I/O端口，通過sw指令，輸出對(duì)DE2實(shí)驗(yàn)板上的LED燈CPU內(nèi)部的寄存器，寫入到外部設(shè)備的相應(yīng)控制寄存器（或可直接連接利用自己編寫的程序代碼，在自己設(shè)計(jì)的CPU上，實(shí)現(xiàn)對(duì)板載輸入開關(guān)或按鍵的狀態(tài)輸入，并將判別或處理結(jié)果，利用板載LED燈或7段LED數(shù)碼管顯示出來。例如，將一路4bit二進(jìn)制輸入與另一路4bit二進(jìn)制輸入相加，利用兩組分別2個(gè)LED數(shù)碼管以10進(jìn)制形式顯示“被加數(shù)”和“加數(shù)”，另外一組LED數(shù)碼管以10進(jìn)制形式顯示“和”等（具體任務(wù)形式不做嚴(yán)格 實(shí)驗(yàn)儀 序主要流程圖。1.采用VerilogHDL在quartus中實(shí)現(xiàn)基本的具有20條MIPS指令的單周期CPU設(shè)計(jì)。 AlteraDE1-SOC實(shí)驗(yàn)板1示波器1數(shù)字萬用表1

puter_sim.rar90%代碼，我們需要補(bǔ)全剩余代碼。各1，按照該圖補(bǔ)全真值表再分別補(bǔ)全alu.v與cu.v，完善這兩個(gè)構(gòu)件的功能。圖1:單周期alu.v的補(bǔ)alucaluc123456789modulealu(a,b,aluc,s,z);input[31:0]a,b;input[3:0]aluc;output[31:0]s; z;reg[31:0]s; zalways@(aorboraluc //casex(aluc4’bx000:s=a+b //x0004’bx100:s=a?b //x1004’bx001:s=a&b //x0014’bx101:s=a|b //x1014’bx010:s=a^b //x0104’bx110:s=b<<16 //x110LUI:imm<<164’b0011:s=b<<a //0011SLL:rd<?(rt<<sa4’b0111:s=b>>a; //0111SRL:rd<?(rt>>sa)(logical) 4’b1111:s=$signed(b)>>>a; //1111SRA:rd<?(rt>>sa)(arithmetic) default:s=0 if(s== z=1 elsez=0 26sc_cu.vmodulesc_cu(op,func,z,wmem,wreg,regrt,m2reg,aluc,shimodulesc_cu(op,func,z,wmem,wreg,regrt,m2reg,aluc,shift,aluimm,pcsource,jal,sext); [5:0]op,func; z; wreg,regrt,jal,m2reg,shift,aluimm,sextoutput[3:0]aluc //seealu.123456 output[1:0]pcsource;//mux4x32nextpc(p4,adr,ra,jpc,pcsource,) wirer_type=~|op9 wirei_add=r_type&func[5]&~func[4]&~func[3] ~func[2]&~func[1]&~func[0] // wirei_sub=r_type&func[5]&~func[4]&~func[3] ~func[2]&func[1]&~func[0] // pleasecompletethedeletedcode wirei_and=r_type&func[5]&~func[4]&~func[3]&func[2]&~func[1]&~func[0]; wirei_or=r_type&func[5]&~func[4]&~func[3]&func[2]&~func[1]&func[0]; wirei_xor=r_type&func[5]&~func[4]&~func[3]&func[2]&func[1]&~func[0]; wirei_sll=r_type&~func[5]&~func[4]&~func[3]&~func[2]&~func[1]&~func[0]; wirei_srl=r_type&~func[5]&~func[4]&~func[3]&~func[2]&func[1]&~func[0]; wirei_sra=r_type&~func[5]&~func[4]&~func[3]&~func[2]&func[1]&func[0]; wirei_jr=r_type&~func[5]&~func[4]&func[3]&~func[2]&~func[1]&~func[0]; wirei_addi=~op[5]&~op[4]&op[3]&~op[2]&~op[1]&~op[0];// wirei_andi=~op[5]&~op[4]&op[3]&op[2]&~op[1]&~op[0];// wirei_ori ~op[5]&~op[4]&op[3]&op[2]&~op[1]&op[0] wirei_xori ~op[5]&~op[4]&op[3]&op[2]&op[1]&~op[0] wire op[5]&~op[4]&~op[3]&~op[2]&op[1]&op[0] wire =op[5]&~op[4]&op[3]&~op[2]&op[1]&op[0] wirei_beq=~op[5]&~op[4]&~op[3]&op[2]&~op[1]&~op[0] wirei_bne=~op[5]&~op[4]&~op[3]&op[2]&~op[1]&op[0] wirei_l =~op[5] ~op[4]&op[3]&op[2]&op[1] op[0] wire =~op[5]&~op[4]&~op[3]&~op[2]&op[1]&~op[0] wirei_jal=~op[5]&~op[4]&~op[3]&~op[2]&op[1]&op[0] assignpcsource[1]=i_jr|i_j|i_jal assignpcsource[0]=(i_beq&z)|(i_bne&~z)|i_j|i_jal assignwreg=i_add|i_sub|i_and| | ii_sll|i_srl|i_sra|i_addi|i_andii_ori|i_xori|i_lw|i_l |i_jalassignaluc[3]assignaluc[2]=i_lui;assignaluc[1]assignaluc[0]i_sra|i_sw //completebyyourself|i_or|i_srl||i_ori|i_bne|i_beq|i_sll|i_srl||i_or|i_andi||i_xori|i_lui|i_sll|i_srl|i_sraassignshif =i_sll|i_srl|i_sraassignaluimm=i_addi|i_ori|i_andi|i_xori|i_lw|i_sw|i_lui; completebyyourself.assignsext =i_addi|i_lw|i_sw|i_beq|i_bne;assignwmem =i_sw;assign i_lwassignregrt =i_addi|i_ori|i_andi|i_xori|i_lw|i_sw|i_lui;assignjal =i_jal;I/O將I/O地址空間設(shè)計(jì)為內(nèi)存地址空間的一部分，即I/O地址和內(nèi)存地址統(tǒng)一編址，CPU在內(nèi)存MEM和I/O端口時(shí)，采用相同的指令，區(qū)自己的范圍）的識(shí)別進(jìn)行區(qū)分。如圖2，利用address[7]，來區(qū)分是RAM還是I/O。本實(shí)驗(yàn)中，若address[7:2]為 則分別為out_port0、out_port1、out_port2，輸出端口地址：80h，84h，88h；若address[7:2]為1100002、1100012則為in_port0、in_port1，輸入////moduleio_input_reg(addr,io_clk,io_read_data,in_port0,in_port1)io_input_muxio_imput_mux2x32(in_reg0,in_reg1,addr[7:2],io_read_data)23[31:0[31:0addrio_clkin_port0,in_port1[31:0io_read_data[31:0in_reg0 //input[31:0in_reg1 //input56789圖2:I/Oalwaysalways@(posedgeio_clkin_reg0<=in_port0;in_reg1<=in_port1moduleio_input_mux(a0,a1,sel_addr,y)[31:0a0,a1[5:0sel_addr[31:0y[31:0yalways@case(sel_addr6’b110000:y=a06’b110001:y=a1////moduleio_output_reg(addr,datain,write_io_enable,io_clk,clrn,out_port0,out_port1,out_port2);input[31:0]addr,dataininputwrite_io_enable,io_clk;inputclrn;//resetsignal.ifnecessary,canusethissignaltoresettheoutputto0.output[31:0]out_port0,out_port1,out_port2;reg[31:0]out_port0,out_port1,out_port2always@(posedgeio_clkornegedgeclrn)if(clrn==0)out_port0<=0;out_port1<=0;out_port2<=0;23456789elseelseif(write_io_enable==1)case(addr[7:2])6’b100000:out_port0<=datain;//80h6’b100001:out_port1<=datain;//84h6’b100010:out_port2<=datain;//88hputer.v的補(bǔ)computer的設(shè)計(jì)，將之computercpu設(shè)計(jì)自己的時(shí)鐘頻率，此次實(shí)驗(yàn)中將去原頻率的半頻。為方便輸入輸出數(shù)據(jù)在FPGA板上的顯示，通過整除取puterputer(resetn,mem_clk,in_port0,in_port1,out_port0,out_port1out_port2,HEX0,HEX1,HEX2,HEX3,HEX4,HEX5)//inputresetn,clock,mem_clk;inputresetn,mem_clk;wireclockinput[3:0 in_port0 in_port1//output[31:0]pc,inst,aluout,memout;wire[31:0]pc,inst,aluout,memout;//imem_clk,dmem_clkwireimem_clk,dmem_clkoutput[31:0 out_port0,out_port1,out_port2//reg[31:0]tmp0,tmp1,tmp2wire[31:0]out_port0,out_port1,out_port2; [31:0]data; wmem;//allthese”wire”sareusedtoconnectorinterfacethecpu,dmem,imemandsoon.outputwire[6:0]half_frequencyhf(resetn,mem_clk,clock)sc_cpucpu(clock,resetn,inst,memout,pc,wmem,aluout,data)module//23456789 sc_instmemimem(pc,inst,clock,mem_clk,imem_clk); instructionmemory. sc_datamemdmem(aluout,data,memout,wmem,clock,mem_clk,dmem_clk,resetn,in_port0,in_port1,out_port0,out_port1,out_port2);//datamemory.reg[3:0]low0,high0,,high1,low2,high2alwayshigh0=out_port0/10low0=out_port0?*10high1=out_port1/10low1=out_port1?*10high2=out_port2/10low2=out_port2?*10sevensegs0(low0,HEX4)sevensegs1(high0,HEX5)sevensegs2(low1,HEX2)sevensegs3(high1,HEX3)sevensegs4(low2,HEX0)sevensegs5(high2,HEX1)4547modulehalf_frequency(resetn,mem_clk,clock) inputresetn,mem_clk outputclock regclock initia clock=0 always@(posedge if(~resetn clock<=0 clock<=~clock 6163modulesevenseg(in,sevenseg)65input[3:0]in66output[6:0]sevenseg67reg[6:0]sevenseg69initia70 sevenseg=07273alwayscase(in4’h0sevenseg[6:0=7’;4’h1sevenseg[6:0=7’;4’h2sevenseg[6:0=7’;4’h3sevenseg[6:0=7’;4’h4sevenseg[6:0=7’;4’h5sevenseg[6:0=7’;4’h6sevenseg[6:0=7’;4’h7sevenseg[6:0=7’;4’h8sevenseg[6:0=7’;4’h9sevenseg[6:0=7’;4sevenseg[6:0=7’;4sevenseg[6:0=7’;4sevenseg[6:0=7’;4sevenseg[6:0=7’;4sevenseg[6:0