經(jīng)典word整理文檔，僅參考，雙擊此處可刪除頁(yè)眉頁(yè)腳。本資料屬于網(wǎng)絡(luò)整理，如有侵權(quán)，請(qǐng)聯(lián)系刪除，謝謝！數(shù)字系統(tǒng)設(shè)計(jì)課程設(shè)計(jì)設(shè)計(jì)題目：基于FPGA的簡(jiǎn)單計(jì)時(shí)器一、功能說明與實(shí)現(xiàn)方法1、實(shí)驗(yàn)項(xiàng)目設(shè)計(jì)一個(gè)60秒倒計(jì)時(shí)器2、設(shè)計(jì)要求（功能說明）晶振輸入信號(hào)：48MHZ時(shí)鐘信號(hào)開機(jī)60秒開始倒計(jì)時(shí)，用兩只七段數(shù)碼管顯示，計(jì)時(shí)結(jié)束時(shí)顯示00，同時(shí)產(chǎn)生報(bào)警輸出，報(bào)警信號(hào)用指示燈或蜂鳴器顯示。3、實(shí)驗(yàn)思路根據(jù)設(shè)計(jì)指標(biāo)，將電路設(shè)計(jì)分成5個(gè)模塊：分頻器，計(jì)數(shù)器，掃描計(jì)數(shù)，數(shù)據(jù)選擇器，七段顯示譯碼器二、基于VHDL方法的設(shè)計(jì)方案1、系統(tǒng)需求和解決方案計(jì)劃在項(xiàng)目開始設(shè)計(jì)時(shí)，首先要確定系統(tǒng)的需求并發(fā)展出一個(gè)針對(duì)這些需求的計(jì)劃。晶振本設(shè)計(jì)所用為48MHz的晶振信號(hào)。分頻器對(duì)晶體振蕩器產(chǎn)生的時(shí)鐘信號(hào)進(jìn)行分頻，產(chǎn)生時(shí)間基準(zhǔn)信號(hào)。本設(shè)計(jì)中將48MHz的信號(hào)分頻成1KHz和1Hz的基準(zhǔn)頻率，1KHz的用于計(jì)數(shù)掃描達(dá)到視覺殘留效果，1Hz的用于倒計(jì)時(shí)計(jì)數(shù)。計(jì)數(shù)器對(duì)1Hz時(shí)間基準(zhǔn)脈沖進(jìn)行計(jì)數(shù)，完成倒計(jì)時(shí)功能。輸入輸出信號(hào)定義seg:outstd_logic_vector(1downto0);--數(shù)碼管位選信號(hào)定義dig:outstd_logic_vector(6downto0)--數(shù)碼管段選信號(hào)定義中間信號(hào)定義定義1Hz分頻器的計(jì)數(shù)信號(hào)，定義1KHz分頻器的計(jì)數(shù)信號(hào)，signaldata1:std_logic_vector(3downto0):="0000";--定義個(gè)位數(shù)的計(jì)數(shù)信號(hào)signaldata2:std_logic_vector(3downto定義十位數(shù)的計(jì)數(shù)信號(hào)signaldata:std_logic_vector(3downto0);signalclk_1:std_logic:='0';定義七段譯碼器的輸入信號(hào)定義1Hz時(shí)鐘信號(hào)signalclk_1k:std_logic:='0';signalsel:STD_LOGIC_vector(1downto0):="00";定義1KHz時(shí)鐘信號(hào)定義計(jì)數(shù)掃描信號(hào)beginprocess(clk_in)begin分頻器1，產(chǎn)生1KHz時(shí)鐘ifrising_edge(clk_in)thenifcnt_1k=48000thencnt_1k<=1;計(jì)數(shù)到48000時(shí)從1重新開始計(jì)數(shù)clk_1k<=notclk_1k;--1KHz時(shí)鐘跳變elsecnt_1k<=cnt_1k+1;endif;endif;endprocess;process(clk_in)begin分頻器2，產(chǎn)生1Hz時(shí)鐘，用于計(jì)數(shù)ifrising_edge(clk_in)thenifcnt=48000000thencnt<=1;計(jì)數(shù)到48000000時(shí)從1重新開始計(jì)數(shù)--1Hz時(shí)鐘跳變clk_1<=notclk_1;elsecnt<=cnt+1;endif;endif;endprocess;process(clk_1)begin計(jì)數(shù)器模塊ifrising_edge(clk_1)thenifdata1="0000"thendata1<="1001";data2<=data2-1;else在1Hz時(shí)鐘的上升沿如果各位上數(shù)字減到0從9開始重新減十位上數(shù)字自減1data1<=data1-1;endif;ifdata1="0000"anddata2="0000"thenalarm<='0';倒計(jì)時(shí)結(jié)束使能報(bào)警信號(hào)計(jì)時(shí)結(jié)束時(shí)顯示00data1<="0000";data2<="0000";endif;endif;endprocess;process(clk_1k,sel)數(shù)據(jù)掃描計(jì)數(shù)器，用于產(chǎn)生選擇兩個(gè)數(shù)碼管點(diǎn)亮的信號(hào)beginifrising_edge(clk_1k)thenifsel="10"thensel<="01";采用1KHz信號(hào)觸發(fā)，達(dá)到視覺暫留要求elsesel<=sel+1;endif;交替產(chǎn)生兩個(gè)數(shù)碼管選通信號(hào)endif;endprocess;process(sel,data1,data2)數(shù)據(jù)選擇器，用于分時(shí)段選擇兩個(gè)數(shù)碼管顯示的數(shù)據(jù)begincaseseliswhen"10"=>data<=data1;when"01"=>data<=data2;whenothers=>data<="1111";endcase;右邊數(shù)碼管選通時(shí)，送個(gè)位數(shù)左邊邊數(shù)碼管選通時(shí)，送十位數(shù)其他情況不顯示任何數(shù)字seg<=sel;endprocess;process(data)begin七段顯示譯碼器，產(chǎn)生數(shù)字0~9的顯示信號(hào)casedataiswhen"0000"=>dig<="1000000";when"0001"=>dig<="1111001";when"0010"=>dig<="0100100";when"0011"=>dig<="0110000";when"0100"=>dig<="0011001";when"0101"=>dig<="0010010";when"0110"=>dig<="0000010";when"0111"=>dig<="1111000";when"1000"=>dig<="0000000";when"1001"=>dig<="0010000";whenothers=>dig<="1111111";endcase;顯示數(shù)字’0‘顯示數(shù)字’