TimingAnalysis&

SignalSimulation

onPCSystemsByPierreLeeatARIMA4/16/2002HoldCommonClockDataTransferD0D1D2D0D1D2ClockDriverDrivingReceivingTcoFlightTimeSetup1234DefiningTcoDinClockOutput

BufferInternal

LogicRL=50WClockrisest=0VmeasTcoLoadforTcomeasurement(fromdatabook)Tco=timefromclockrisetoVmeasintotestloadComponentsofTcoDinClockOutput

BufferInternal

LogicRL=50WClockrisest=0VmeasTcoInternaldelay=fromclock

risetothepointwheretheoutputbeginstoswitchExternal(buffer)delay=how

longthebuffertakestodrivethe

referenceloadtoVmeasForSignalIntegrityPurposes...Output

BufferInternal

LogicnotmodeledRL=50WBufferswitchesatt=0VmeasBufferDelayLoadforTcomeasurement(fromdatabook)It’sallintheMath...DrivingReceivingTcoFlightTime1234???t=0ClockJitterClockDriverCycle1Cycle2ClockJitteroccurswhentheclockperiodvariesfromoneperiodtothenextUsuallycausedbyPLLinstabilityintheclockdriverJitterincreases/decreasestheclockperiod,decreasingtheeffectiveclockcycleClockSkewD0D1D2ClockDriverD0D1D2t=0t=1t=2OccurswhendifferentdevicesseetheclocktransitionatdifferenttimesIncreases/decreasestheapparentclockcycle.Dependingonwhichdevicesaredriving/receivingReducestheeffectiveclockcycleBusClockCycleBudgetingForeachDriverReceiverpath:Tflightmax<ClockPeriod-Driver(Tcomax)-Skew-Jitter-Crosstalk-Receiver(Setup)Tflightmin>Receiver(Hold)-Driver(Tcomin)+Skew+CrosstalkDriver(Tcomax)Tflightmax+/-Jitter+/-SkewReceiver(Setup)<ClockPeriodDriver(Tcomin)Tflightmin+/-Skew>Receiver(Hold)+/-Crosstalk+/-CrosstalkCommonClockBusExampleIntelPentium-ProreferencedesignProcessor/ChipsetBus

(GTL+,66MHz)IntelGTL+DesignGuidelinesDefiningDeviceTimingTimingstakenfrom“AC(dynamic)Specifications”sectionsofInteldatasheetsMostdatasheetsavailableviaWWWImportantparametersClockDataValid

forGTL+BusSetup/Holdrequirements

forGTL+signalsPLLJitter(ifspec’d)PentiumPro440FX(timingsfrom440LX)DeterminingFlightTimesTflightmax=4.50nsTflightmin=0.45nsSignalWavePropagationFlighttimet1=L/cc6.5in/nsTflightmax=4.50ns

Tflightmin=0.45ns29in>L>3inRiskOhm’slaw?i=(va-vb)/Rtracei→∞when

Rtrace→0ModeloftransmissionlineSignalWavePropagationFlighttimet1=L/cv1=VoltagePartitionforR0&z0

R0z0

v1v2v2=VoltagePartitionforR0&RL

RLImpedanceChangeLayerchangeReferenceplanecrossingTracesplittingSeriescomponentConnectorPullhigh&pulldownImpedanceChangeLayerchangeReferenceplanecrossingTracesplittingSeriescomponentConnectorPullhighSchematicsvs.LayoutVccMicrostripSectionhtwerZo=f(w,h,t,er)Zo=Characteristicimpedance(W)w =Widthoftrace(mils)t =Thicknessoftrace(mils)h=Thicknessofdielectriclayer(mils)er

=Dielectricconstantofthedielectriclayer

DesignedbyBoardDesignerOnlyfewoptionsavailableofferedbyPCBvendorImpedanceVerificationbyTDRImpedanceVerificationbyTDRImpedanceMeasuredbyHP54754AFlip-ChipPackageIBISModel

I/OBufferInformationSpec.Output

BufferInternal

LogicnotmodeledSimulationby3comLowVoltageCMOSUn-terminatedTerminatedLowVoltageCMOSUn-terminatedTerminatedClockgen.WaveformIDEWaveformCrosstalkWhentracesareclosetogether,achangeincurrentflowinonetracewillcausecurrenttoflowinanadjacenttraceAggressortracesinducecurrentsinadjacentvictimtracesChangesincurrentflowonlyoccurduringtheaggressor’srisingandfallingedgesCrosstalkNoCrosstalkImpactsofCrosstalkCrosstalkcausesswitchingnoisetoappearonvictimtracesthatwouldotherwisebequietCrosstalkdegradesthesystemnoisebudgetwhenitoccursbetweensignalsthatarenotpartofthesamesignalgroupSincecrosstalkonlyoccurswhendriversareswitching,themagnitudeofcrosstalkbetweenbusbitsisusuallynotimportantAggressorVictimCrosstalk-inducednoiseElectricalModelforCrosstalkCrosstalk-ImpactonBusTimingCrosstalkbetweenadjacentbusbitsaffectsedgespeed(andthereforeflighttime)Denserroutingmakesbetteruseofboardspace,butattheexpenseoflargervariationsinflighttimePre-layoutcrosstalkanalysishelpsthedesignermakethebesttradeoffbetweenroutingdensityandsignalintegrityEvenModeReferenceOddModeD0D1D2D0D1D2D0D1D2D0D1D2ExampleofCrosstalkRiskinmassproductionPCB’sstatisticalqualityDrivingstrengthvariationinchipsetPassivecomponent’squalityTemperaturevariationMonteCarloAnalysisAriskanalysisinsteadofanalyticalmethodUsedincomplicatesystemsortoomanyparametersSuitableformassproductionmodelsExampleofMonteCarloMonteCarloforClockSignalC