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AV-51001

2020.11.20

PowerManagement

PowerManagement

LeveragingtheFPGAarchitecturalfeatures,processtechnologyadvancements,andtransceiversthatare

designedforpowerefficiency,theArriaVdevicesconsumelesspowerthanpreviousgenerationArriaV

FPGAs:

?Totaldevicecorepowerconsumption—lessbyupto50%.

?Transceiverchannelpowerconsumption—lessbyupto50%.

Additionally,ArriaVdevicescontainseveralhardIPblocks,includingPCIeGen1,Gen2,andGen3,GbE,

SRIO,GPON,andCPRIprotocols,thatreducelogicresourcesanddeliversubstantialpowersavingsofup

to25%lesspowerthanequivalentsoftimplementations.

DocumentRevisionHistory

Document

Version

Changes

2020.11.20Removedinformationaboutpartialreconfiguration.

2020.06.15

?Removedthe"ES"fromthelistofoptionalsuffixfromthefollowingfigures:

?SampleOrderingCodeandAvailableOptionsforArriaVGXDevices

?SampleOrderingCodeandAvailableOptionsforArriaVGTDevices

?SampleOrderingCodeandAvailableOptionsforArriaVSXDevices

?SampleOrderingCodeandAvailableOptionsforArriaVSTDevices

?UpdatedtheRoHSinformationtoincludethe"P"suffixinthesampleorderingcodeforall

theArriaVdevices.

2019.04.16

UpdatedRoHSandoptionalsuffixinformationinsampleorderingcodeandavailableoptions

diagramsforalltheArriaVdevices.

Date

Version

Changes

December

2015

2015.12.21

?UpdatedRoHSandoptionalsuffixinformationinsampleordering

codeandavailableoptionsdiagramsforArriaVGXandGTdevices.

?ChangedinstancesofQuartusIItoQuartusPrime.

January2015

2015.01.23

?UpdatedpackagedimensionforArriaVGZH780packagefrom

29mmto33mm.

?Updateddual-coreARMCortex-A9MPCoreprocessormaximum

frequencyfrom800MHzto1.05GHz.

ArriaVDeviceOverview

SendFeedback

AV-51001

2020.11.20

DocumentRevisionHistory

Date

Version

Changes

December

2013

2013.12.26

?10-GbpsEthernet(10GbE)PCSandInterlakenPCSareforArriaV

GZonly.

?Removed"Preliminary"textsfromOrderingCodefigures,Maximum

Resources,PackagePlanandI/OVerticalMigrationtables.

?AddedlinktoAlteraProductSelectorforeachdevicevariant.

?Addedleadedpackageoptions.

?Removedthenote"ThenumberofPLLsincludesgeneral-purpose

fractionalPLLsandtransceiverfractionalPLLs."forallPLLsinthe

MaximumResourceCountstable.

?CorrectedFPGAGPIOforArriaVSXB3andB5aswellasArriaV

STD3andD5F896packagefrom170to250.

?CorrectedFPGAGPIOforArriaVSXB3andB5aswellasArriaV

STD3andD5F1152packagefrom350to385.

?CorrectedFPGAGPIOforArriaVSXB3andB5aswellasArriaV

STD3andD5F1517packagefrom528to540.

?CorrectedLVDSTransmitterforArriaVSXB3andB5aswellas

ArriaVSTD3andD5devicesfrom121to120.

?AddedlinkstoAltera'sExternalMemorySpecEstimatortooltothe

topicslistingtheexternalmemoryinterfaceperformance.

?Addedx2forPCIeGen3,Gen2,andGen1.

August2013

2013.08.19

?RemovedthenoteaboutthePCIehardIPontherightsideofthe

deviceintheF896packageoftheArriaVGXvariant.Thesedevices

donothavePCIehardIPontherightside.

?Addedtransceiverspeedgrade6totheavailableoptionsoftheArria

VSXvariant.

?CorrectedthemaximumLVDStransmitterchannelcountsforthe

ArriaVGXA1andA3devicesfrom68to67.

?CorrectedthemaximumFPGAGPIOcountforArriaVSTD5

devicesfrom540to528.

June2013

2013.06.03

?Removedstatementsabo

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