1Chapter6

CombinationalLogicDesignPractices

(組合邏輯設(shè)計實踐)DocumentationStandardandCircuitTiming(文檔標(biāo)準(zhǔn)和電路定時)CommonlyUsedMSICombinationalLogicDevice(常用的中規(guī)模組合邏輯器件)DigitalLogicDesignandApplication(數(shù)字邏輯設(shè)計及應(yīng)用)26.5Encoder（編碼器）BinaryEncoderA0A1A2I0I1I71000000000001000000001001000000100001000001100001000100000001001010000001011000000001111I0I1I2I3I4I5I6I7A2A1A0(3位二進(jìn)制編碼器的真值表)

2nInputsnOut-putsTruthTablefora8-to-3EncoderDigitalLogicDesignandApplication(數(shù)字邏輯設(shè)計及應(yīng)用)3Guarantee:TheInputsareassertedatmostoneatatime.(前提：任何時刻只有一個輸入端有效。)1000000000001000000001001000000100001000001100001000100000001001010000001011000000001111I0I1I2I3I4I5I6I7A2A1A0(3位二進(jìn)制編碼器的真值表)6.5Encoder（編碼器）TruthTablefora8-to-3EncoderDigitalLogicDesignandApplication(數(shù)字邏輯設(shè)計及應(yīng)用)4A0=I1+I3+I5+I7A1=I2+I3+I6+I7A2=I4+I5+I6+I7Trouble:WhenmorethanOneInputsareasserted?(問題：當(dāng)某時刻出現(xiàn)多個輸入有效？)Priority（優(yōu)先級）1000000000001000000001001000000100001000001100001000100000001001010000001011000000001111I0I1I2I3I4I5I6I7A2A1A0(3位二進(jìn)制編碼器的真值表)6.5Encoder（編碼器）TruthTablefora8-to-3EncoderDigitalLogicDesignandApplication(數(shù)字邏輯設(shè)計及應(yīng)用)5PriorityEncoder

(優(yōu)先編碼器)A2A1A0IDLEI7I6I5I4I3I2I1I0ChangeI0～I(xiàn)7to

H0～H7,MakeSuretheInputsareassertedatmostoneatatime.

(將I0～I(xiàn)7轉(zhuǎn)換為H0～H7，保證其中，任何時刻只有一個有效)Highest-Priority(數(shù)大優(yōu)先)6.5Encoder（編碼器）DigitalLogicDesignandApplication(數(shù)字邏輯設(shè)計及應(yīng)用)6PriorityEncoder

(優(yōu)先編碼器)A2A1A0IDLEI7I6I5I4I3I2I1I0H7=I7H6=I6·I7’H5=I5·I6’·I7’…H0=I0·I1’·I2’·…·I6’·I7’A2=H4+H5+H6+H7A1=H2+H3+H6+H7A0=H1+H3+H5+H7Highest-Priority(數(shù)大優(yōu)先)6.5Encoder（編碼器）DigitalLogicDesignandApplication(數(shù)字邏輯設(shè)計及應(yīng)用)7PriorityEncoder

(優(yōu)先編碼器)A2A1A0IDLEI7I6I5I4I3I2I1I0ChangeI0～I(xiàn)7to

H0～H7,MakeSuretheInputsareassertedatmostoneatatime.

(將I0～I(xiàn)7轉(zhuǎn)換為H0～H7，保證其中，任何時刻只有一個有效)Highest-Priority(數(shù)大優(yōu)先)

TheIDLEOutputisassertedifNoInputsareasserted.(如果沒有輸入有效，則IDLE為1

)

IDLE=I0’·I1’·…·I6’·I7’6.5Encoder（編碼器）DigitalLogicDesignandApplication(數(shù)字邏輯設(shè)計及應(yīng)用)8輸入輸出使能輸出，用于級聯(lián)EO選通輸出GSEI_L有效沒有輸入請求EO_L有效EnableInputsEIEI_L有效有輸入請求GS_L有效圖6-48表6-27The74x148PriorityEncoder(優(yōu)先級編碼器74x148)DigitalLogicDesignandApplication(數(shù)字邏輯設(shè)計及應(yīng)用)9A2A1A0GSEOEII7I0A2A1A0GSEOEII7I0Q15_LQ8_LQ7_LQ0_LY0Y1Y2Y3GS2個74x148級聯(lián)為16－4優(yōu)先編碼器DigitalLogicDesignandApplication(數(shù)字邏輯設(shè)計及應(yīng)用)10輸入：由864，需8片74x148每片優(yōu)先級不同（怎樣實現(xiàn)？）保證高位無輸入時，次高位才工作

——高位芯片的EO端接次高位芯片的EI端用8-3優(yōu)先編碼器74x148級聯(lián)為64-6優(yōu)先編碼器A2A1A0GSEOEII7I0片間優(yōu)先級的編碼

——利用第9片74x148

每片的GS端接到第9片的輸入端

第9片的輸出作為高3位（RA5～RA3）片內(nèi)優(yōu)先級片間優(yōu)先級輸出：6位低3位高3位8片輸出A2～A0通過或門作為最終輸出的低3位RA2～RA0DigitalLogicDesignandApplication(數(shù)字邏輯設(shè)計及應(yīng)用)11設(shè)計判定優(yōu)先級電路：（利用74x148）8個輸入I0～I(xiàn)7高電平有效，I7優(yōu)先級最高地址輸出A2～A0，高電平有效如果沒有輸入有效，A2～A0為111且輸出IDLE有效I7I0A2A1A0IDLEA2A1A0GSEOEII7I074x148題6.52DigitalLogicDesignandApplication(數(shù)字邏輯設(shè)計及應(yīng)用)答案對嗎？如果有誤，如何修改？126.6Three-StateDevices

(三態(tài)器件)Three-StateBuffer(Three-StateDriver)

[三態(tài)緩沖器（三態(tài)驅(qū)動器）]Figure6-51ThreeStates:High(1)，Low(0)，Hi-Z

(三種狀態(tài)：高電平，低電平，高阻態(tài)）DigitalLogicDesignandApplication(數(shù)字邏輯設(shè)計及應(yīng)用)136.6Three-StateDevices

(三態(tài)器件)

Three-StateDeviceallowMultipleSourcestoShareaSingle“PartyLine“AslongasOnlyOnedevice“talk”ontheLineatatime（三態(tài)器件允許多個信號源共享單個“同線”，條件是每次只有一個器件工作）(Figure6-52)DigitalLogicDesignandApplication(數(shù)字邏輯設(shè)計及應(yīng)用)14ABCG1G2AG2BY0Y1Y2Y3Y4Y5Y6Y774x138EN1EN2_LEN3_LSSRC0SSRC1SSRC2沖突（fighting）利用使能端進(jìn)行時序控制三態(tài)器件允許信號共享單個“同線”（partyline）典型的三態(tài)器件，進(jìn)入高阻態(tài)比離開高阻態(tài)快P0P1P7SDATADigitalLogicDesignandApplication(數(shù)字邏輯設(shè)計及應(yīng)用)15EN1EN2_L,EN3_Lmax(tpLZmax,tpHZmax)min(tpZLmin,tpZHmin)SSRC[2:0]01237SDATAP0P1P2P3P7DeadTime(截止時間)DigitalLogicDesignandApplication(數(shù)字邏輯設(shè)計及應(yīng)用)Figure6-53166.6Three-StateDevices

(三態(tài)器件)74x245：雙向傳輸數(shù)據(jù)，低電平使能

DIR決定傳輸方向74x541：兩個公共使能端，低電平使能，施密特觸發(fā)輸入，輸出不反相（圖6-546-55）

StandardSSIandMSIThree-StateBuffer

(標(biāo)準(zhǔn)SSI和MSI三態(tài)緩沖器)（圖6-566-57）DigitalLogicDesignandApplication(數(shù)字邏輯設(shè)計及應(yīng)用)17A1A8G1G2Y1Y874x541DB[0:7]A1A8G1G2Y1Y874x541NotationofDataBus（數(shù)據(jù)總線的表示法）

圖6－55DigitalLogicDesignandApplication(數(shù)字邏輯設(shè)計及應(yīng)用)18A1B1DIRTransferDatainEitherDirectionsByUsingThree-StateTransceiver(利用三態(tài)緩沖器實現(xiàn)數(shù)據(jù)雙向傳送)BusTransceiver(總線收發(fā)

圖6－56)DIRG_LDigitalLogicDesignandApplication(數(shù)字邏輯設(shè)計及應(yīng)用)196.7Multiplexer（多路復(fù)用器）DigitalSwitch,Multi-Switch,DataSelector(又稱數(shù)據(jù)開關(guān)、多路開關(guān)、數(shù)據(jù)選擇器)（縮寫：MUX）

UnderSelectControllingSignals,SelectOneoftheMulti-InputstotheOutput

(在選擇控制信號的作用下，從多個輸入數(shù)據(jù)中選擇其中一個作為輸出。)DigitalLogicDesignandApplication(數(shù)字邏輯設(shè)計及應(yīng)用)206.7Multiplexer（多路復(fù)用器）ENSELD0Dn-1YEnable使能Select選擇n個1位數(shù)據(jù)源數(shù)據(jù)輸出（1位）ENSELD0Dn-1YEnable(使能)Select(選擇)NDataSources(n個b位數(shù)據(jù)源)DataOutput(數(shù)據(jù)輸出)（b位）DigitalLogicDesignandApplication(數(shù)字邏輯設(shè)計及應(yīng)用)21EN_LCBAYY_L1XXX0000000100100011010001010110011101D0D0’D1D1’D2D2’D3D3’D4D4’D5D5’D6D6’D7D7’(8輸入1位多路復(fù)用器)TruthTablefora74x151ABC8-Input,1-bitMultiplexerDigitalLogicDesignandApplication(數(shù)字邏輯設(shè)計及應(yīng)用)22輸入G_LS1X000100001A2A3A4A1B2B3B4B(2輸入4位多路復(fù)用器)TruthTablefora74x157輸出1Y2Y3Y4Y1A2A3A4A2-Input,4-bitMultiplexerDigitalLogicDesignandApplication(數(shù)字邏輯設(shè)計及應(yīng)用)231G_L2G_LBA1Y2Y11XX000000010010001101000101011001111000100110101011

001C02C01C12C11C22C21C32C31C001C101C201C30

02C002C102C202C3(4輸入2位多路復(fù)用器74x153真值表)雙4選1AB1G2GTruthTablefora74x1534-Input,2-bitMultiplexer24ExpandingMultiplexers

(擴(kuò)展多路復(fù)用器)ExpandingBit(擴(kuò)展位)HowtoRealize8-Input,16-bitMultiplexer?

(如何實現(xiàn)8輸入，16位多路復(fù)用器？)From8-Input,1-bitto8-Input,16-bit

(由8輸入1位8輸入16位)Need1674x151,EachChipProcess1-bit

(需要16片74x151，每片處理輸入輸出中的1位)DigitalLogicDesignandApplication(數(shù)字邏輯設(shè)計及應(yīng)用)25ExpandingMultiplexers

(擴(kuò)展多路復(fù)用器)ExpandingBit(擴(kuò)展位)Select-InputsConnecttoC,B,AofEachChip(選擇端連接到每片的C,B,A)Note:TheFanoutAbilityofSelectfield

(注意：選擇端的扇出能力)（驅(qū)動16個負(fù)載）ENYYABCD0D7DigitalLogicDesignandApplication(數(shù)字邏輯設(shè)計及應(yīng)用)26ExpandingInputs(擴(kuò)展數(shù)據(jù)輸入端的數(shù)目)Howtorealize32-Input,1-bitMultiplexer

(如何實現(xiàn)32輸入，1