IntroductiontoSequentialDevices:LatchesAboutSequentialDevicesIfwepress1,2,3…tochooseachannel1,2,3…,thatiscombinationalcircuit(組合電路).Ifwepress“up”,“down”,thatisasequentialcircuit(時(shí)序電路).Foritsoutputdependsonnotonlyinputbutcurrentstate.DigitalLogicBistable(雙穩(wěn)態(tài))CircuitsDigitalLogicTwoStableOutputs：Generally,weusethestateofQtorepresentthestateofthewholecircuit.ing：Withoutanyinputs,circuitcannotchangeitsownstate.TherebesomefeedbackSet-ResetLatch(NORstructure)DigitalLogicLogicsymbolcircuitSet-ResetLatch(SR

Latch,SR鎖存器)Latch:門(mén)閂Circuit&LogicsymbolTheinputSmeansSet(置位端,置1端),RmeansReset(復(fù)位端,置0端).QnrepresentsPresentState(當(dāng)前狀態(tài)),Qn+1=NextState(下一次狀態(tài))DescriptionofSRLatches(NOR)DigitalLogic

StateTransitionTruthTable(狀態(tài)轉(zhuǎn)移真值表)011=>Q0=>Q’SRQnQn+1effect0000NoChange0011NoChange0100Reset0110Reset1001Set1011Set110NANotAllowed111NANotAllowedDescriptionofSRLatches(NOR)DigitalLogic100=>Q1=>Q’SRQnQn+1effect0000NoChange0011NoChange0100Reset0110Reset1001Set1011Set110NANotAllowed111NANotAllowed

StateTransitionTruthTable(狀態(tài)轉(zhuǎn)移真值表)DescriptionofSRLatches(NOR)DigitalLogic11uncertainSRQnQn+1effect0000NoChange0011NoChange0100Reset0110Reset1001Set1011Set110NANotAllowed111NANotAllowed

StateTransitionTruthTable(狀態(tài)轉(zhuǎn)移真值表)DescriptionofSRLatches(NOR)DigitalLogic01=>0No

change,

WHY?SRQnQn+1effect0000NoChange0011NoChange0100Reset0110Reset1001Set1011Set110NANotAllowed111NANotAllowed

StateTransitionTruthTable(狀態(tài)轉(zhuǎn)移真值表)DescriptionofSRLatches(NOR)DigitalLogic01=>0No

changeSRQnQn+1effect0000NoChange0011NoChange0100Reset0110Reset1001Set1011Set110NANotAllowed111NANotAllowed

StateTransitionTruthTable(狀態(tài)轉(zhuǎn)移真值表)DescriptionofSRLatches(NOR)DigitalLogic

StateTransitionDiagram(狀態(tài)轉(zhuǎn)移圖)SRQnQn+1effect0000NoChange0011NoChange0100Reset0110Reset1001Set1011Set110NANotAllowed111NANotAllowed0110010dd00：Q’sstate10：Transitionconditions(S=1,R=0)DescriptionofSRLatches(NOR)DigitalLogic

CharacteristicEquation(特征方程)(constraintcondition)110001101000110××SQn+1RQn1SRQnQn+1effect0000NoChange0011NoChange0100Reset0110Reset1001Set1011Set110NANotAllowed111NANotAllowedSet-resetlatch(NAND)DigitalLogic

Circuit&LogicSymbol

ExcitingTruthTable

Notallowed0110

nochange00011011CharacteristicEquationofSR-Latch(NAND)DigitalLogicHowtokeepinmind(especiallyconditions)：InSR-Latch(NANDstructure),weshouldanalyzetheinput“0”,sowedon’thopethetwoinputsarebothzero,thatistwosayInput1+Input2=1;However,InSR-Latch(NORstructure),weshouldanalyzetheinput“1”,sowedon’thopethetwoinputsareboth1,thatistwosayRS=0;(constraintcondition約束條件)

CharacteristicEquation(特征方程)SomeconclusionsDigitalLogic

StateofSR-Latch:State0,State1

PresentState&NextState“0”態(tài)“1”態(tài)orAbnormal(非正常態(tài))statesPresentState(現(xiàn)態(tài)),usuallyrepresentedbyQnNextState(次態(tài)),usuallyrepresentedbyQn+1Example:SRLatch(NOR)DigitalLogic

Example00WiththegivenR,S(NOR)’sTimingdiagram,trytogivetheoutputdiagram.AtfirstQis0.NC1001NA00011011RS

010010000100GatedLatches(鐘控鎖存器)WeshouldcontroltheoutputofSR-Latch.Justaswehopein“decoders”Thinkaboutit,howcanweaddcontrolfunctiontothedevicedecoderEnablePinMethod:byaddinganinputtoANDgateDigitalLogicGatedSR-Latch(鐘控SR鎖存器)DigitalLogic

circuit&logicsymbol

SRLatchClockPulseCP=0:outputofG3,G4arestate1=>stateholdCP=1:outputofG3,G4areS’,R’=>workasusualGatedSR-LatchDigitalLogic

CharacteristicEquationSohowtocontrol?GatedSR-LatchDigitalLogic

?GatedSR-LatchDigitalLogic

CharacteristicEquationInputsOutputDescriptionCPSRQQn+10dd00Hold0dd1110000Workswell10011101001011011001110111110d1111dGatedSR-LatchDigitalLogic

CharacteristicEquationContrastofSR-Latch&GatedSR-LatchDigitalLogic(a)SR-Latch

(b)gatedSR-LatchWecansee,SR-Latchescanresponsetoinputatanytime,butGatedSR-Latchesonlyresponsetoinputduringhighvoltagelevel.GatedDelayLatch(鐘控D鎖存器)DigitalLogic

Circuit&logicsymbolCPDQQn+1Function0d00Hold0d111000Store010101101Store11111TheDLatchisconstructedonlybyconnectinginputDtoRandD’toS.ThuswecanfindthatSR=DD’=0GatedD-LatchDigitalLogicCharacteristicEquation

CPDQQ*Function0d00Hold0d111000Store010101101Store11111Wecansee,thenextstateofDLatchequalsthecurrentinput,andthatiswhyitiscalledDelayLatch.GatedJKLatch(鐘控JK鎖存器)DigitalLogic

Circuit&logicsymbolTheJKLatchisconstructedbyconnectingsomeoutputstotheinputNANDgates.Asshowninthecircuitabove.Why?andwhatisthepurposeGatedJK-LatchDigitalLogic

CharacteristicEquation

Asfarastheconstraintconditionisconcerned:SR=JKQn(Qn)’=0.Sonootherconditionsareneeded.Exercise:derivethecharacteristicequationofJKLatch.GatedTLatch(鐘控T鎖存器)DigitalLogic

Circuits&logicsymbolTLatchcanberegardedasaJKLatchwithJ=K=TGatedTLatchDigitalLogic

CharacteristicEquation

TruthTableT

Qn

Qn+1

000110110110ItlookslikeXORLogic.Whatdoesitlooklike?Whichlogic?GatedT’LatchDigitalLogic

Circuit&logicsymbolT’LatchcanbeconsideredasaTLatchwhereT=1.StudyNotesofGatedLatchesDigitalLogicLatchesCharacteristicEquationsSRDJKTT’LatchesEquationDescription/FunctionRS-DDmeansDelay,NextStateisCurrent:DJKWholefunction:Hold(保持);Set(置1);Reset(置0);Reverse(取反)TXORlogic:Reverse(T=1);Hold(T=0)T’ReverseStudyNotesofGatedLatchesDigitalLogicThinkAboutItDigitalLogicTrytofindoutinwhichcasehasJKLatchthefunction:hold,set,