1、Chapter 3: Node Architecture,WSN Node/Cyber-Physical System,Sensors capture phenomena in the physical world. Signal conditioning prepare captured signals for further use. Analog-to-digital conversion translates analog signal into digital signal. Digital signal is processed and output is often given

2、to an actuator.,WSN Node for ETH Zurich,Vibration sensor board: vibration detection and control.,WSN Node for ETH Zurich,WSN board: vibration and temperature sensing.,Accelerometer, Temperature sensor, USART and I2C, MCU-ATmega1384P, Communication-Zigbee.,WSN Node for ETH Zurich,WSN board: vibration

3、 and temperature sensing.,Outline,Node Architecture,Wireless sensor nodes are the essential building blocks in a wireless sensor network sensing, processing, and communication stores and executes the communication protocols as well as data processing algorithms The node consists of sensing, processi

4、ng, communication, and power subsystems trade-off between flexibility and efficiency both in terms of energy and performance,Node Architecture,Architecture of a wireless sensor node.,Node Architecture,Circuit schematic of a wireless sensor node.,Outline,The Sensing Subsystem,Sensing: technique to ga

5、ther information about physical objects or areas. Sensor (transducer): object performing a sensing task; converting one form of energy in the physical world into electrical energy. Examples of sensors from biology: the human body eyes: capture optical information (light). ears: capture acoustic info

6、rmation (sound). nose: captures olfactory information (smell). skin: captures tactile information (shape, texture).,Sensor Classifications,Analog-to-Digital Converter,ADC converts the output of a sensor - which is a continuous, analog signal - into a discrete, digital signal. It requires two steps:

7、the analog signal has to be quantized.,Quantization Error,Analog-to-Digital Converter,The analog signal has to be quantized. resolution of ADC - an expression of the number of bits that can be used to encode the digital output.,where Q is the resolution in volts per step (volts per output code); Epp

8、 is the peak-to-peak analog voltage; M is the ADCs resolution in bits,Analog-to-Digital Converter,The sampling frequency Nyquist rate does not suffice because of noise and transmission error,Oversampling is necessary for WSN.,Analog-to-Digital Converter,ADC converts the output of a sensor - which is

9、 a continuous, analog signal - into a digital signal. the analog signal has to be quantized allowable discrete values is influenced : (a) by the frequency and magnitude of the signal (b) by the available processing and storage resources 2. the sampling frequency Nyquist rate does not suffice because

10、 of noise and transmission error resolution of ADC - an expression of the number of bits that can be used to encode the digital output,Outline,The Processor Subsystem,The processor subsystem interconnects all the other subsystems and some additional peripheries its main purpose is to execute instruc

11、tions pertaining to sensing, communication, and self-organization It consists of processor chip nonvolatile memory - stores program instructions active memory - temporarily stores the sensed data internal clock,The Processor Subsystem,Mini-system Power supply, MCU, Clock, Reset, Debugger,Architectur

12、al Overview,The processor subsystem can be designed by employing one of the three basic computer architectures Von Neumann architecture Harvard architecture Super-Harvard (SHARC) architecture,Von Neumann Architecture,Von Neumann architecture provides a single memory space - storing program instructi

13、ons and data provides a single bus - to transfer data between the processor and the memory Slow processing speed - each data transfer requires a separate clock,Von Neumann Architecture,Devices with Von Neumann architecture The 8051 microcontrollers (MCS-51) Intel P8051，Atmel AT89C/S, etc. System-on-

14、chip (SoC) wireless controllers. TI CC2540， CC2530，etc.,Harvard Architecture,Harvard architecture provides separate memory spaces - storing program instructions and data each memory space is interfaced with the processor with a separate data bus program instructions and data can be accessed at the s

15、ame time a special single instruction, multiple data (SIMD) operation, a special arithmetic operation and a bit reverse supports multi-tasking operating systems; but does not provide virtual memory protection,Harvard Architecture,ALU: Arithmetic Logical Unit.,Super-Harvard Architecture,Super-Harvard

16、 architecture (best known: SHARC) an extension of the Harvard architecture adds two components to the Harvard architecture: internal instruction cache - temporarily store frequently used instructions - enhances performance an underutilized program memory can be used as a temporary relocation place f

17、or data Direct Memory Access (DMA) costly CPU cycles can be invested in a different task program memory bus and data memory bus accessible from outside the chip,Super-Harvard Architecture,Architecture comparison： ,Von Neumann Architecture single memory， single bus,Harvard Architecture multiple memor

18、y， multiple bus,Super-Harvard Architecture multiple memory， multiple bus，Cache， DMA,The Processor Subsystem,Processor classifications： Microcontroller Digital Signal Processor Application-specific Integrated Circuit Field Programmable Gate Array,Microcontroller,Advantages: suitable for building comp

19、utationally less intensive, standalone applications, because of its compact construction, small size, low-power consumption, and low cost high speed of the programming and eases debugging, because of the use of higher-level programming languages Disadvantages: not as powerful and as efficient as som

20、e custom-made processors (such as DSPs and FPGAs),Microcontroller,Applications: Simple sensing tasks Large scale deployments Low power and cost ,Digital Signal Processor,The main function: process discrete signals with digital filters filters minimize the effect of noise on a signal or enhance or mo

21、dify the spectral characteristics of a signal while analog signal processing requires complex hardware components, digital signal processors (DSP) requires simple adders, multipliers, and delay circuits DSPs are highly efficient most DSPs are designed with the Harvard Architecture,Digital Signal Pro

22、cessor,Advantages: powerful and complex digital filters can be realized with commonplace DSPs useful for applications that require the deployment of nodes in harsh physical settings (where the signal transmission suffers corruption due to noise and interference and, hence, requires aggressive signal

23、 processing) Disadvantage: some tasks require protocols (and not numerical operations) that require periodical upgrades or modifications (i.e., the networks should support flexibility in network reprogramming),The Processor Subsystem,Processor classifications： Microcontroller Digital Signal Processo

24、r Application-specific Integrated Circuit Field Programmable Gate Array,Application-specific Integrated Circuit,ASIC is an IC that can be customized for a specific application Two types of design approaches: full-customized and half-customized full-customized IC: some logic cells, circuits, or layou

25、t are custom made in order to optimize cell performance includes features which are not defined by the standard cell library expensive and long design time half-customized ASICs are built with logic cells that are available in the standard library in both cases, the final logic structure is configur

26、ed by the end user - an ASIC is a cost efficient solution, flexible, and reusable,Application-specific Integrated Circuit,Advantages: relatively simple design; can be optimized to meet a specific customer demand multiple microprocessor cores and embedded software can be designed in a single cell Dis

27、advantage: high development costs and lack of re-configurability,Design,Verification Simulation,Synthesis,Physical Layout,ASIC,Application-specific Integrated Circuit,Application: ASICs are not meant to replace microcontrollers or DSPs but to complement them handle rudimentary and low-level tasks to

28、 decouple these tasks from the main processing subsystem,Field Programmable Gate Array (FPGA),The distinction between ASICs and FPGAs is not always clear FPGAs are more complex in design and more flexible to program FPGAs are programmed electrically, by modifying a packaged part programming is done

29、with the support of circuit diagrams and hardware description languages, such as VHDL and Verilog,Field Programmable Gate Array (FPGA),Advantages: higher bandwidth compared to DSPs flexible in their application support parallel processing work with floating point representation greater flexibility o

30、f control Disadvantages: complex the design and realization process is costly,Design,Simulation,Synthesis,FPGA Layout,FPGA prototype,Comparison,Working with a micro-controller is preferred if the design goal is to achieve flexibility Working with the other mentioned options is preferred if power con

31、sumption and computational efficiency is desired DSPs are expensive, large in size and less flexible; they are best for signal processing, with specific algorithms FPGAs are faster than both microcontrollers and digital signal processors and support parallel computing; but their production cost and

32、the programming difficulty make them less suitable,Comparison,ASICs have higher bandwidths; they are the smallest in size, perform much better, and consume less power than any of the other processing types; but have a high cost of production owing to the complex design process,Outline,Node Architect

33、ure,Architecture of a wireless sensor node.,Communication interface,Communication Interfaces,Fast and energy efficient data transfer between the subsystems of a wireless sensor node is vital however, the practical size of the node puts restriction on system buses communication via a parallel bus is

34、faster than a serial transmission a parallel bus needs more space Therefore, considering the size of the node, parallel buses are never supported,Communication Interfaces,Parallel Bus vs. Serial Bus,Communication Interfaces,The choice is often between serial interfaces : Serial Peripheral Interface

35、(SPI) General Purpose Input/Output (GPIO) Secure Data Input/Output (SDIO) Inter-Integrated Circuit (I2C) Universal Asynchronous Receiver/Transmitter (UART) Among these, the most commonly used buses are SPI, I2C and UART,Serial Peripheral Interface,SPI (Motorola, in the mid-80s) high-speed, full-dupl

36、ex synchronous serial bus does not have an official standard, but use of the SPI interface should conform to the implementation specification of others - correct communication,3-axis accelerometer with SPI.,Zigbee module with SPI.,Serial Peripheral Interface,The SPI bus defines four pins: MOSI (Mast

37、erOut/SlaveIn) used to transmit data from the master to the slave when a device is configured as a master MISO (MasterIn/SlaveOut) SCLK (Serial Clock) used by the master to send the clock signal that is needed to synchronize transmission used by the slave to read this signal synchronize transmission

38、 CS (Chip Select) - communicate via the CS port,Serial Peripheral Interface,SS: Chip Select,Serial Peripheral Interface,Both master and slave devices hold a shift register Every device in every transmission must read and send data SPI supports a synchronous communication protocol the master and the

39、slave must agree on the timing master and slave should agree on two additional parameters clock polarity (CPOL) - defines whether a clock is used as high- or low-active clock phase (CPHA) - determines the times when the data in the registers is allowed to change and when the written data can be read

40、,Serial Peripheral Interface,Serial Peripheral Interface,Inter-Integrated Circuit,The I2C bus was developed in the early 1980s by Philips Semiconductors. Every device type that uses I2C must have a unique address that will be used to communicate with a device In earlier versions, a 7 bit address was

41、 used, allowing 112 devices to be uniquely addressed - due to an increasing number of devices, it is insufficient Currently I2C uses 10 bit addressing I2C is a multi-master half-duplex synchronous serial bus only two bidirectional lines: (unlike SPI, which uses four) Serial Clock (SCL) Serial Data (

42、SDA),Inter-Integrated Circuit,Since each master generates its own clock signal, communicating devices must synchronize their clock speeds a slower slave device could wrongly detect its address on the SDA line while a faster master device is sending data to a third device I2C requires arbitration bet

43、ween master devices wanting to send or receive data at the same time no fair arbitration algorithm rather the master that holds the SDA line low for the longest time wins the medium,Inter-Integrated Circuit,The aim of I2C is to minimize costs for connecting devices accommodating lower transmission s

44、peeds I2C defines two speed modes: a fast-mode - a bit rate of up to 400Kbps high-speed mode - a transmission rate of up to 3.4 Mbps they are downwards compatible to ensure communication with older components,Inter-Integrated Circuit,Rp is a pullup resistor.,Inter-Integrated Circuit,（a）Old I2C proto

45、col.,（b）New I2C protocol.,Comparison,Communication Interfaces - Summary,Buses are essential highways to transfer data due to the concern for size, only serial buses can be used serial buses demand high clock speeds to gain the same throughput as parallel buses serial buses can also be bottlenecks (e

46、.g., Von Neumann architecture) or may not scale well with processor speed (e.g., I2C) Delays due to contention for bus access become critical, for example, if some of the devices act unfairly and keep the bus occupied,Outline,Prototypes,iMote,XYZ Node,Hogthrob,The IMote Node Architecture,The IMote s

47、ensor node architecture is a multi-purpose architecture, consisting of : a power management subsystem a processor subsystem a sensing subsystem a communication subsystem an interfacing subsystem,The IMote Node Architecture,The IMote Node Architecture,A multiple-sensor board contains : a 12-bit, four

48、 channels ADC a high-resolution temperature/humidity sensor a low-resolution digital temperature sensor a light sensor the I2C bus is used to connect low data rate sources the SPI bus is used to interface high data rate sources,Imote2 upgraded from IMote.,The IMote Node Architecture,The sensing subs

49、ystem of the IMote architecture,The IMote Node Architecture,The processing subsystem provides main processor (microprocessor) operates in low voltage (0.85V) and low frequency (13MHz) mode Dynamic Voltage Scaling (104MHz - 416MHz) sleep and deep sleep modes thus enabling low power operation coproces

50、sor (a DSP) accelerates multimedia operations - computation intensive,Target applications include industrial vibration, structural monitoring, acoustic and visual monitoring.,The XYZ Node Architecture,Consists of the four subsystems: power subsystem communication subsystem mobility subsystem sensor subsystem,/enalab/XYZ/,The XYZ Node Architecture,The XYZ Node Architecture,The processor subsystem is based on the ARM7TDMI core microcontroller fmax = 58MHz two different modes (32bits and 16