1、 單片機(jī)英文參考文獻(xiàn)篇一：5-單片機(jī)+外文文獻(xiàn)+英文文獻(xiàn)+外文翻譯中英對照 AT89C51的介紹 （原文出處：http：/resource/） 描述 AT89C51是一個(gè)低電壓，高性能CMOS8位單片機(jī)帶有4K字節(jié)的可反復(fù)擦寫的程序存儲(chǔ)器（PENROM）。和128字節(jié)的存取數(shù)據(jù)存儲(chǔ)器（RAM），這種器件采用ATMEL公司的高密度、不容易丟失存儲(chǔ)技術(shù)生產(chǎn)，并且能夠與MCS-51系列的單片機(jī)兼容。片內(nèi)含有8位中央處理器和閃爍存儲(chǔ)單元，有較強(qiáng)的功能的AT89C51單片機(jī)能夠被應(yīng)用到控制領(lǐng)域中。 功能特性 AT89C51提供以下的功能標(biāo)準(zhǔn)：4K字節(jié)閃爍存儲(chǔ)器，128字節(jié)隨機(jī)存取數(shù)據(jù)存儲(chǔ)器，32個(gè)I/O

2、口，2個(gè)16位定時(shí)/計(jì)數(shù)器，1個(gè)5向量兩級中斷結(jié)構(gòu)，1個(gè)串行通信口，片內(nèi)震蕩器和時(shí)鐘電路。另外，AT89C51還可以進(jìn)行0HZ的靜態(tài)邏輯操作，并支持兩種軟件的節(jié)電模式。閑散方式停止中央處理器的工作，能夠允許隨機(jī)存取數(shù)據(jù)存儲(chǔ)器、定時(shí)/計(jì)數(shù)器、串行通信口及中斷系統(tǒng)繼續(xù)工作。掉電方式保存隨機(jī)存取數(shù)據(jù)存儲(chǔ)器中的內(nèi)容，但震蕩器停止工作并禁止其它所有部件的工作直到下一個(gè)復(fù)位。 引腳描述 VCC：電源電壓 GND：地 P0口： P0口是一組8位漏極開路雙向I/O口，即地址/數(shù)據(jù)總線復(fù)用口。作為輸出口時(shí)，每一個(gè)管腳都能夠驅(qū)動(dòng)8個(gè)TTL電路。當(dāng)“1”被寫入P0口時(shí)，每個(gè)管腳都能夠作為高阻抗輸入端。P0口還能夠在

3、訪問外部數(shù)據(jù)存儲(chǔ)器或程序存儲(chǔ)器時(shí)，轉(zhuǎn)換地址和數(shù)據(jù)總線復(fù)用，并在這時(shí)激活內(nèi)部的上拉電阻。P0口在閃爍編程時(shí)，P0口接收指令，在程序校驗(yàn)時(shí)，輸出指令，需要接電阻。 沈陽航空工業(yè)學(xué)院電子工程系畢業(yè)設(shè)計(jì)（外文翻譯） P1口： P1口一個(gè)帶內(nèi)部上拉電阻的8位雙向I/O口，P1的輸出緩沖級可驅(qū)動(dòng)4個(gè)TTL電路。對端口寫“1”，通過內(nèi)部的電阻把端口拉到高電平，此時(shí)可作為輸入口。因?yàn)閮?nèi)部有電阻，某個(gè)引腳被外部信號拉低時(shí)輸出一個(gè)電流。閃爍編程時(shí)和程序校驗(yàn)時(shí)，P1口接收低8位地址。 P2口： P2口是一個(gè)內(nèi)部帶有上拉電阻的8位雙向I/O口，P2的輸出緩沖級可驅(qū)動(dòng)4個(gè)TTL電路。對端口寫“1”，通過內(nèi)部的電阻把端口

4、拉到高電平，此時(shí)，可作為輸入口。因?yàn)閮?nèi)部有電阻，某個(gè)引腳被外部信號拉低時(shí)會(huì)輸出一個(gè)電流。在訪問外部程序存儲(chǔ)器或16位地址的外部數(shù)據(jù)存儲(chǔ)器時(shí)，P2口送出高8位地址數(shù)據(jù)。在訪問8位地址的外部數(shù)據(jù)存儲(chǔ)器時(shí)，P2口線上的內(nèi)容在整個(gè)運(yùn)行期間不變。閃爍編程或校驗(yàn)時(shí)，P2口接收高位地址和其它控制信號。 P3口： P3口是一組帶有內(nèi)部電阻的8位雙向I/O口，P3口輸出緩沖故可驅(qū)動(dòng)4個(gè)TTL電路。對P3口寫如“1”時(shí)，它們被內(nèi)部電阻拉到高電平并可作為輸入端時(shí)，被外部拉低的P3口將用電阻輸出電流。 P3口除了作為一般的I/O口外，更重要的用途是它的第二功能，如下表所示：P3- 2 -RST： 復(fù)位輸入。當(dāng)震蕩器工

5、作時(shí)，RET引腳出現(xiàn)兩個(gè)機(jī)器周期以上的高電平將使單片機(jī)復(fù)位。 ALE/PROG： 當(dāng)訪問外部程序存儲(chǔ)器或數(shù)據(jù)存儲(chǔ)器時(shí)，ALE輸出脈沖用于鎖存地址的低8位字節(jié)。即使不訪問外部存儲(chǔ)器，ALE以時(shí)鐘震蕩頻率的1/16輸出固定的正脈沖信號，因此它可對輸出時(shí)鐘或用于定時(shí)目的。要注意的是：每當(dāng)訪問外部數(shù)據(jù)存儲(chǔ)器時(shí)將跳過一個(gè)ALE脈沖時(shí)，閃爍存儲(chǔ)器編程時(shí)，這個(gè)引腳還用于輸入編程脈沖。如果必要，可對特殊寄存器區(qū)中的8EH單元的D0位置禁止ALE操作。這個(gè)位置后只有一條MOVX和MOVC指令A(yù)LE才會(huì)被應(yīng)用。此外，這個(gè)引腳會(huì)微弱拉高，單片機(jī)執(zhí)行外部程序時(shí)，應(yīng)設(shè)置ALE無效。 ： 程序儲(chǔ)存允許輸出是外部程序存儲(chǔ)器

6、的讀選通信號，當(dāng)AT89C51由外部程序存儲(chǔ)器讀取指令時(shí)，每個(gè)機(jī)器周期兩次PSEN 有效，即輸出兩個(gè)脈沖。在此期間，當(dāng)訪問外部數(shù)據(jù)存儲(chǔ)器時(shí)，這兩次有效的PSEN 信號不出現(xiàn)。 EA/VPP： 外部訪問允許。欲使中央處理器僅訪問外部程序存儲(chǔ)器，EA端必須保持低電平。需要注意的是：如果加密位LBI被編程，復(fù)位時(shí)內(nèi)部會(huì)鎖存EA端狀態(tài)。如EA端為高電平，CPU則執(zhí)行內(nèi)部程序存儲(chǔ)器中的指令。閃爍存儲(chǔ)器編程時(shí)，該引腳加上+12V的編程允許電壓VPP，當(dāng)然這必須是該器件是使用12V編程電壓VPP。 XTAL1：震蕩器反相放大器及內(nèi)部時(shí)鐘發(fā)生器的輸入端。 XTAL2：震蕩器反相放大器的輸出端。 時(shí)鐘震蕩器 A

7、T89C51中有一個(gè)用于構(gòu)成內(nèi)部震蕩器的高增益反相放大器，引腳XTAL1和XTAL2分別是該放大器的輸入端和輸出端。這個(gè)放大器與作為反饋元件的片外石英晶體或陶瓷諧振器一起構(gòu)成自然震蕩器。 外接石英晶體及電容C1，C2接在放大器的反饋回路中構(gòu)成并聯(lián)震蕩電路。對外接電容C1，C2雖然沒有十分嚴(yán)格的要求，但 沈陽航空工業(yè)學(xué)院電子工程系畢業(yè)設(shè)計(jì)（外文翻譯） 電容容量的大小會(huì)輕微影響震蕩頻率的高低、震蕩器工作的穩(wěn)定性、起振的難易程序及溫度穩(wěn)定性。如果使用石英晶體，我們推薦電容使用30PF10PF，而如果使用陶瓷振蕩器建議選擇40PF10PF。用戶也可以采用外部時(shí)鐘。采用外部時(shí)鐘的電路如圖示。這種情況下，

8、外部時(shí)鐘脈沖接到XTAL1端，即內(nèi)部時(shí)鐘發(fā)生器的輸入端，XTAL2則懸空。由于外部時(shí)鐘信號是通過一個(gè)2分頻觸發(fā)器后作為內(nèi)部時(shí)鐘信號的，所以對外部時(shí)鐘信號的占空比沒有特殊要求，但最小高電平持續(xù)時(shí)間和最大的低電平持續(xù)時(shí)間應(yīng)符合產(chǎn)品技術(shù)條件的要求。內(nèi)部振蕩電路 外部振蕩電路 閑散節(jié)電模式 AT89C51有兩種可用軟件編程的省電模式，它們是閑散模式和掉電工作模式。這兩種方式是控制專用寄存器PCON中的PD和IDL位來實(shí)現(xiàn)的。PD是掉電模式，當(dāng)PD=1時(shí)，激活掉電工作模式，單片機(jī)進(jìn)入掉電工作狀態(tài)。IDL是閑散等待方式，當(dāng)IDL=1，激活閑散工作狀態(tài)，單片機(jī)進(jìn)入睡眠狀態(tài)。如需要同時(shí)進(jìn)入兩種工作模式，即PD

9、和IDL同時(shí)為1，則先激活掉電模式。在閑散工作模式狀態(tài)，中央處理器CPU保持睡眠狀態(tài)，而所有片內(nèi)的外設(shè)仍保持激活狀態(tài)，這種方式由軟件產(chǎn)生。此時(shí)，片內(nèi)隨機(jī)存取數(shù)據(jù)存儲(chǔ)器和所有特殊功能寄存器的內(nèi)容保持不變。閑散模式可由任何允許的中斷請求或硬件復(fù)位終止。終止閑散工作模式的方法有兩種，一是任何一條被允許中斷的事件被激活，IDL被硬件清除，即刻終止閑散工作模式。程序會(huì)首先影響中斷，進(jìn)入中斷服務(wù)程序，執(zhí)行完中斷服務(wù)程序，并緊隨RETI指令后，下一條要執(zhí)行 - 4 - 的指令就是使單片機(jī)進(jìn)入閑散工作模式，那條指令后面的一條指令。二是通過硬件復(fù)位也可將閑散工作模式終止。需要注意的是：當(dāng)由硬件復(fù)位來終止閑散工作

10、模式時(shí)，中央處理器CPU通常是從激活空閑模式那條指令的下一條開始繼續(xù)執(zhí)行程序的，要完成內(nèi)部復(fù)位操作，硬件復(fù)位脈沖要保持兩個(gè)機(jī)器周期有效，在這種情況下，內(nèi)部禁止中央處理器CPU訪問片內(nèi)RAM，而允許訪問其他端口，為了避免可能對端口產(chǎn)生的意外寫入：激活閑散模式的那條指令后面的一條指令不應(yīng)是一條對端口或外部存儲(chǔ)器的寫入指令。 掉電模式 在掉電模式下，振蕩器停止工作，進(jìn)入掉電模式的指令是最后一條被執(zhí)行的指令，片內(nèi)RAM和特殊功能寄存器的內(nèi)容在中指掉電模式前被凍結(jié)。退出掉電模式的唯一方法是硬件復(fù)位，復(fù)位后將從新定義全部特殊功能寄存器但不改變RAM中的內(nèi)容，在VCC恢復(fù)到正常工作電平前，復(fù)位應(yīng)無效切必須保

11、持一定時(shí)間以使振蕩器從新啟動(dòng)并穩(wěn)定工作。 閑散和掉電模式外部引腳狀態(tài)。 程序存儲(chǔ)器的加密 AT89C51可使用對芯片上的三個(gè)加密位LB1，LB2，LB3進(jìn)行編程（P）或不編程（U）得到如下表所示的功能：篇二：單片機(jī)畢業(yè)參考英文文獻(xiàn)及翻譯 附錄：英文技術(shù)資料翻譯 英文原文： Structure and function of the MCS-51 series Structure and function of the MCS-51 series one-chip computer MCS-51 is a name of a piece of one-chip computer series w

12、hich Intel Company produces. This company introduced 8 top-grade one-chip computers of MCS-51 series in 1980 after introducing 8 one-chip computers of MCS-48 series in 1976. It belong to a lot of kinds this line of one-chip computer the chips have,such as 8051, 8031, 8751, 80C51BH, 80C31BH,etc., the

13、ir basic composition, basic performance and instruction system are all the same. 8051 daily representatives- 51 serial one-chip computers . An one-chip computer system is made up of several following parts: ( 1) One microprocessor of 8 (CPU). ( 2) At slice data memory RAM (128B/256B),it use not depo

14、sitting not can reading /data that write, such as result not middle of operation, final result and data wanted to show, etc. ( 3) Procedure memory ROM/EPROM (4KB/8KB ), is used to preserve the procedure , some initial data and form in slice. But does not take ROM/EPROM within some one-chip computers

15、, such as 8031 , 8032, 80C ,etc. ( 4) Four 8 run side by side I/O interface P0 four P3, each mouth can use as introduction , may use as exporting too. ( 5) Two timer / counter, each timer / counter may set up and count in the way, used to count to the external incident, can set up into a timing way

16、too, and can according to count or result of timing realize the control of the computer. ( 6) Five cut off cutting off the control system of the source . ( 7) One all duplexing serial I/O mouth of UART (universal asynchronous receiver/transmitter (UART) ), is it realize one-chip computer or one-chip

17、 computer and serial communication of computer to use for. ( 8) Stretch oscillator and clock produce circuit, quartz crystal finely tune electric capacity need outer. Allow oscillation frequency as 12 megahertas now at most. Every the above-mentioned part was joined through the inside data bus .Amon

18、gthem, CPU is a core of the one-chip computer, it is the control of the computer and command centre, made up of such parts as arithmetic unit and controller , etc. The arithmetic unit can carry on 8 persons of arithmetic operation and unit ALU of logic operation while including one, the 1 storing de

19、vice temporarilies of 8, storing device 2 temporarily, 8s accumulation device ACC, register B and procedure state register PSW, etc. Person who accumulate ACC count by 2 input ends entered of checking etc. temporarily as one operation often, come from person who store 1 operation is it is it make op

20、eration to go on to count temporarily , operation result and loopback ACC with another one. In addition, ACC is often regarded as the transfer station of data transmission on 8051 inside . The same as general microprocessor, it is the busiest register. Help remembering that agreeing with A expresses

21、 in the order. The controller includes the procedure counter , the order is depositted, the order decipher, the oscillator and timing circuit, etc. The procedure counter is made up of counter of 8 for two, amounts to 16. It is a byte address counter of the procedure in fact, the content is the next

22、IA that will carried out in PC. The content which changes it can change the direction that the procedure carries out . Shake the circuit in 8051 one-chip computers, only need outer quartz crystal and frequency to finely tune the electric capacity, its frequency range is its 12MHZ of This pulse signa

23、l, as 8051 basic beats of working, namely the minimum unit of time. 8051 is the same as other computers, the work in harmony under the control of the basic beat, just like an orchestra according to the beat play that is commanded. There are ROM (procedure memory , can only read ) and RAM in 8051 sli

24、ces (data memory, can is it can write ) two to read, they have each independent memory address space, dispose way to be the same with general memory of computer. Procedure 8051 memory and 8751 slice procedure memory capacity 4KB, address begin from 0000H, used for preserving the procedure and form c

25、onstant. Data 8051- 8751 8031 of memory data memory 128B, address false 00FH, use for middle result to deposit operation, the data are stored temporarily and the data are buffered etc. In RAM of this 128B, there is unit of 32 byteses that can be appointed as the job register, this and general microp

26、rocessor is different, 8051 slice RAM and job register rank one formation the same toarrange the location. It is not very the same that the memory of MCS-51 series one-chip computer and general computer disposes the way in addition. General computer for first address space, ROM and RAM can arrange i

27、n different space within the range of this address at will, namely the addresses of ROM and RAM, with distributing different address space in a formation. While visiting the memory, corresponding and only an address Memory unit, can ROM, it can be RAM too, and by visiting the order similarly. This k

28、ind of memory structure is called the structure of Princeton. 8051 memories are divided into procedure memory space and data memory space on the physics structure, there are four memory spaces in all: The procedure stores in one and data memory space outside data memory and one in procedure memory s

29、pace and one outside one, the structure forms of this kind of procedure device and data memory separated form data memory, called Harvard structure. But use the angle from users, 8051 memory address space is divided into three kinds: (1) In the slice, arrange blocks of FFFFH , 0000H of location , in

30、 unison outside the slice (use 16 addresses). (2) The data memory address space outside one of 64KB, the address is arranged from 0000H 64KB FFFFH (with 16 addresses ) too to the location. (3) Data memory address space of 256B (use 8 addresses). Three above-mentioned memory space addresses overlap,

31、for distinguishing and designing the order symbol of different data transmission in the instruction system of 8051: CPU visit slice, ROM order spend MOVC , visit block RAM order uses MOVX outside the slice, RAM order uses MOV to visit in slice. 8051 one-chip computer have four 8 walk abreast I/O por

32、t, call P0, P1, P2 and P3. Each port is 8 accurate two-way mouths, accounts for 32 pins altogether. Every one I/O line can be used as introduction and exported independently. Each port includes a latch (namely special function register ), one exports the driver and a introduction buffer . Make data

33、can latch when outputting, data can buffer when making introduction , but four function of passway these self-same. Expand among the system of memory outside having slice, four port these may serve as accurate two-way mouth of I/O in common use. Expand among the system of memory outside having slice

34、, P2 mouth see high 8 address off; P0 mouth is a two-way bus, send the introduction of 8 low addresses and data / export in timesharingOutput grade , P3 of mouth , P1 of P1 , connect with inside have load resistance of drawing , every one of they can drive 4 Model LS TTL load to output. As while inp

35、utting the mouth, any TTL or NMOS circuit can drive P1 of 8051 one-chip computers as P3 mouth in a normal way . Because draw resistance on output grade of them have, can open a way collector too or drain-source resistance is it urge to open a way, do not need to have the resistance of drawing outerl

36、y . Mouths are all accurate two-way mouths too. When the conduct is input, must write the corresponding port latch with 1 first . As to 80C51 one-chip computer, port can only offer milliampere of output electric currents, is it output mouth go when urging one ordinary basing of transistor to regard

37、as, should contact a resistance among the port and transistor base , in order to the electricity while restraining the high level from exporting P1P3 Being restored to the throne is the operation of initializing of an one-chip computer. Its main function is to turn PC into 0000H initially , make the

38、 one-chip computer begin to hold the conduct procedure from unit 0000H. Except that the ones that enter the system are initialized normally,as because procedure operate it make mistakes or operate there arent mistake, in order to extricate oneself from a predicament , need to be pressed and restored

39、 to the throne the key restarting too. It is an input end which is restored to the throne the signal in 8051 China RST pin. Restore to the throne signal high level effective , should sustain 24 shake cycle (namely 2 machine cycles ) the above its effective times. If 6 of frequency of utilization bri

40、lliant to shake, restore to the throne signal duration should exceed 4 delicate to finish restoring to the throne and operating. Produce the logic picture of circuit which is restored to the throne the signal: Restore to the throne the circuit and include two parts outside in the chip entirely. Outs

41、ide that circuit produce to restore to the throne signal (RST ) hand over to Schmitts trigger, restore to the throne circuit sample to output , Schmitt of trigger constantly in each S5P2 , machine of cycle in having one more , then just got and restored to the throne and operated the necessary signa

42、l insidly. Restore to the throne resistance of circuit generally, electric capacity parameter suitable for 6 brilliant to shake,can is it restore to the throne signal high level duration greater than 2 machine cycles to guarantee. Being restored to the throne in the circuit is simple, its function i

43、s very important. Pieces of one-chip computer system could normal running,should first check it can restore to the throne not succeeding. Checking and can pop ones head and monitor the pin with the oscillograph tentatively, push and is restored to the throne the key, the wave form that observes and

44、has enough range is exported (instantaneous), can also through is it restore to the throne circuit group holding value carry on the experiment to change. 注：文獻(xiàn)來源 篇三：單片機(jī)基礎(chǔ)外文翻譯參考文獻(xiàn) 單片機(jī)基礎(chǔ)外文翻譯參考文獻(xiàn) (文檔含中英文對照即英文原文和中文翻譯) 原文: Fundamentals of Single-chip Microcomputer Dr. Dobbs MacintoshJournal Abstract The s

45、ingle-chip microcomputer is the culmination of both the development of the digital computer and the integrated circuit arguably the tow most significant inventions of the 20th century . These tow types of architecture are found in single-chipmicrocomputer. Some employ the split program/data memory o

46、f the Harvard architecture, shown in , others follow the philosophy, widely adapted for general-purpose computers and microprocessors, of making no logical distinction between program and data memory as in the Princeton architecture. In general terms a single-chip microcomputer is characterized by t

47、he incorporation of all the units of a computer into a single device. Keyword: Single-chip Microcomputer ROM RAM Programming Algorithm Features ? Compatible with MCS-51? Products ? 4K Bytes of In-System Reprogrammable Flash Memory Endurance: 1,000 Write/Erase Cycles ? Fully Static Operation: 0 Hz to

48、 24 MHz ? Three-level Program Memory Lock ? 128 x 8-bit Internal RAM ? 32 Programmable I/O Lines ? Two 16-bit Timer/Counters ? Six Interrupt Sources ? Programmable Serial Channel ? Low-power Idle and Power-down Modes Description The AT89C51 is a low-power, high-performance CMOS 8-bit microcomputer w

49、ith 4Kbytes of Flash programmable and erasable read only memory (PEROM). The deviceis manufactured using Atmels high-density nonvolatile memory technology and iscompatible with the industry-standard MCS-51 instruction set and pinout. The on-chipFlash allows the program memory to be reprogrammed in-s

50、ystem or by a conventionalnonvolatile memory programmer. By combining a versatile 8-bit CPU with Flashon a monolithic chip, the Atmel AT89C51 is a powerful microcomputer which providesa highly-flexible and cost-effective solution to many embedded controlAT89C51 provides the following standard featur

51、es: 4Kbytes of Flash, 128 bytes of RAM, 32 I/O lines, two 16-bittimer/counters, a five vector two-level interrupt architecture,a full duplex serial port, on-chip oscillator and clock addition, the AT89C51 is designed with static logicfor operation down to zero frequency and supports twosoftware selectable power saving modes. The Idle Modestops the CPU while allowing the RAM, timer/counters,serial port and interrupt system to continue functioning. ThePower-down Mode saves the RAM contents but freezesthe oscillator disabling all other chip functions until the nexthardware reset. Pin Confi