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1、十五計(jì)數(shù)器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;ENTITY fiveteencout ISPORT(clk,reset,enable : IN std_logic; count : OUT std_logic_vector(3 downto 0);END fiveteencout;ARCHITECTURE counter OF fiveteencout ISSIGNAL count_int:std_logic_vector(0 to 3);BEGINPROCESS(clk,reset)

2、BEGINWAIT UNTIL rising_edge(clk);IF reset = 1 THENcount_int 0);ELSIF enable = 1 THENIF(count_int=1110) THENcount_int=0000;ELSEcount_int = count_int 1;-ELSE- NULL ;-IF (count_int=1001) THEN-count_int=0000;END IF;END IF;END PROCESS;count = count_int;- IF (reset=0) then-q=0000;-ELSIF(clkevent and clk=1

3、) THEN-q=q 1;-IF (q=1001) then-q=0000;-END IF;-IF (reset=1)THEN-q=00;-ELSIF-wait until (clkevent and clk=1);-WAIT UNTIL (clkEVENT AND clk = 1);-WAIT UNTIL (clockEVENT AND clock = 1);- q=q 1;-end if;-count=q;- WAIT UNTIL clock = 1;-if (clockevent and clock=1)then-WAIT UNTIL rising_edge(clock);-clocke

4、vent and clock=1;-count = 0;-WAIT UNTIL (clockEVENT AND clock = 1);-WAIT riseedge clock = 1;-if (clockevent and clock=1) then-WAIT UNTIL rising_edge(clock);-count = 1;-WAIT UNTIL (clockEVENT AND clock = 1);-WAIT UNTIL clock = 1;-if (clockevent and clock=1)then-WAIT UNTIL rising_edge(clock);-count =

5、2;-end if;-end if;-end if;- END PROCESS;END counter;十四計(jì)數(shù)器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;ENTITY fourteencout ISPORT(clk,reset,enable : IN std_logic; count : OUT std_logic_vector(3 downto 0);END fourteencout;ARCHITECTURE counter OF fourteencout ISSIGNAL count_

6、int:std_logic_vector(0 to 3);BEGINPROCESS(clk,reset)BEGINWAIT UNTIL rising_edge(clk);IF reset = 1 THENcount_int 0);ELSIF enable = 1 THENIF(count_int=1101) THENcount_int=0000;ELSEcount_int = count_int 1;-ELSE- NULL ;-IF (count_int=1001) THEN-count_int=0000;END IF;END IF;END PROCESS;count = count_int;

7、- IF (reset=0) then-q=0000;-ELSIF(clkevent and clk=1) THEN-q=q 1;-IF (q=1001) then-q=0000;-END IF;-IF (reset=1)THEN-q=00;-ELSIF-wait until (clkevent and clk=1);-WAIT UNTIL (clkEVENT AND clk = 1);-WAIT UNTIL (clockEVENT AND clock = 1);- q=q 1;-end if;-count=q;- WAIT UNTIL clock = 1;-if (clockevent an

8、d clock=1)then-WAIT UNTIL rising_edge(clock);-clockevent and clock=1;-count = 0;-WAIT UNTIL (clockEVENT AND clock = 1);-WAIT riseedge clock = 1;-if (clockevent and clock=1) then-WAIT UNTIL rising_edge(clock);-count = 1;-WAIT UNTIL (clockEVENT AND clock = 1);-WAIT UNTIL clock = 1;-if (clockevent and

9、clock=1)then-WAIT UNTIL rising_edge(clock);-count = 2;-end if;-end if;-end if;- END PROCESS;END counter;十三計(jì)數(shù)器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;ENTITY thireteencout ISPORT(clk,reset,enable : IN std_logic; count : OUT std_logic_vector(3 downto 0);END thireteencou

10、t;ARCHITECTURE counter OF thireteencout ISSIGNAL count_int:std_logic_vector(0 to 3);BEGINPROCESS(clk,reset)BEGINWAIT UNTIL rising_edge(clk);IF reset = 1 THENcount_int 0);ELSIF enable = 1 THENIF(count_int=1100) THENcount_int=0000;ELSEcount_int = count_int 1;-ELSE- NULL ;-IF (count_int=1001) THEN-coun

11、t_int=0000;END IF;END IF;END PROCESS;count = count_int;- IF (reset=0) then-q=0000;-ELSIF(clkevent and clk=1) THEN-q=q 1;-IF (q=1001) then-q=0000;-END IF;-IF (reset=1)THEN-q=00;-ELSIF-wait until (clkevent and clk=1);-WAIT UNTIL (clkEVENT AND clk = 1);-WAIT UNTIL (clockEVENT AND clock = 1);- q=q 1;-en

12、d if;-count=q;- WAIT UNTIL clock = 1;-if (clockevent and clock=1)then-WAIT UNTIL rising_edge(clock);-clockevent and clock=1;-count = 0;-WAIT UNTIL (clockEVENT AND clock = 1);-WAIT riseedge clock = 1;-if (clockevent and clock=1) then-WAIT UNTIL rising_edge(clock);-count = 1;-WAIT UNTIL (clockEVENT AN

13、D clock = 1);-WAIT UNTIL clock = 1;-if (clockevent and clock=1)then-WAIT UNTIL rising_edge(clock);-count = 2;-end if;-end if;-end if;- END PROCESS;END counter;十二計(jì)數(shù)器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;ENTITY twelvecout ISPORT(clk,reset,enable : IN std_logic; count

14、 : OUT std_logic_vector(3 downto 0);END twelvecout;ARCHITECTURE counter OF twelvecout ISSIGNAL count_int:std_logic_vector(0 to 3);BEGINPROCESS(clk,reset)BEGINWAIT UNTIL rising_edge(clk);IF reset = 1 THENcount_int 0);ELSIF enable = 1 THENIF(count_int=1011) THENcount_int=0000;ELSEcount_int = count_int

15、 1;-ELSE- NULL ;-IF (count_int=1001) THEN-count_int=0000;END IF;END IF;END PROCESS;count = count_int;- IF (reset=0) then-q=0000;-ELSIF(clkevent and clk=1) THEN-q=q 1;-IF (q=1001) then-q=0000;-END IF;-IF (reset=1)THEN-q=00;-ELSIF-wait until (clkevent and clk=1);-WAIT UNTIL (clkEVENT AND clk = 1);-WAI

16、T UNTIL (clockEVENT AND clock = 1);- q=q 1;-end if;-count=q;- WAIT UNTIL clock = 1;-if (clockevent and clock=1)then-WAIT UNTIL rising_edge(clock);-clockevent and clock=1;-count = 0;-WAIT UNTIL (clockEVENT AND clock = 1);-WAIT riseedge clock = 1;-if (clockevent and clock=1) then-WAIT UNTIL rising_edg

17、e(clock);-count = 1;-WAIT UNTIL (clockEVENT AND clock = 1);-WAIT UNTIL clock = 1;-if (clockevent and clock=1)then-WAIT UNTIL rising_edge(clock);-count = 2;-end if;-end if;-end if;- END PROCESS;END counter;十一計(jì)數(shù)器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;ENTITY elevencout

18、 ISPORT(clk,reset,enable : IN std_logic; count : OUT std_logic_vector(3 downto 0);END elevencout;ARCHITECTURE counter OF elevencout ISSIGNAL count_int:std_logic_vector(0 to 3);BEGINPROCESS(clk,reset)BEGINWAIT UNTIL rising_edge(clk);IF reset = 1 THENcount_int 0);ELSIF enable = 1 THENIF(count_int=1010

19、) THENcount_int=0000;ELSEcount_int = count_int 1;-ELSE- NULL ;-IF (count_int=1001) THEN-count_int=0000;END IF;END IF;END PROCESS;count = count_int;- IF (reset=0) then-q=0000;-ELSIF(clkevent and clk=1) THEN-q=q 1;-IF (q=1001) then-q=0000;-END IF;-IF (reset=1)THEN-q=00;-ELSIF-wait until (clkevent and

20、clk=1);-WAIT UNTIL (clkEVENT AND clk = 1);-WAIT UNTIL (clockEVENT AND clock = 1);- q=q 1;-end if;-count=q;- WAIT UNTIL clock = 1;-if (clockevent and clock=1)then-WAIT UNTIL rising_edge(clock);-clockevent and clock=1;-count = 0;-WAIT UNTIL (clockEVENT AND clock = 1);-WAIT riseedge clock = 1;-if (cloc

21、kevent and clock=1) then-WAIT UNTIL rising_edge(clock);-count = 1;-WAIT UNTIL (clockEVENT AND clock = 1);-WAIT UNTIL clock = 1;-if (clockevent and clock=1)then-WAIT UNTIL rising_edge(clock);-count = 2;-end if;-end if;-end if;- END PROCESS;END counter;十計(jì)數(shù)器library ieee;use ieee.std_logic_1164.all;use

22、ieee.std_logic_unsigned.all;ENTITY count ISPORT(clk,reset,enable : IN std_logic; count : OUT std_logic_vector(3 downto 0);END count;ARCHITECTURE counter OF count ISSIGNAL count_int:std_logic_vector(0 to 3);BEGINPROCESS(clk,reset)BEGINWAIT UNTIL rising_edge(clk);IF reset = 1 THENcount_int 0);ELSIF en

23、able = 1 THENIF(count_int=1001) THENcount_int=0000;ELSEcount_int = count_int 1;-ELSE- NULL ;-IF (count_int=1001) THEN-count_int=0000;END IF;END IF;END PROCESS;count = count_int;- IF (reset=0) then-q=0000;-ELSIF(clkevent and clk=1) THEN-q=q 1;-IF (q=1001) then-q=0000;-END IF;-IF (reset=1)THEN-q=00;-E

24、LSIF-wait until (clkevent and clk=1);-WAIT UNTIL (clkEVENT AND clk = 1);-WAIT UNTIL (clockEVENT AND clock = 1);- q=q 1;-end if;-count=q;- WAIT UNTIL clock = 1;-if (clockevent and clock=1)then-WAIT UNTIL rising_edge(clock);-clockevent and clock=1;-count = 0;-WAIT UNTIL (clockEVENT AND clock = 1);-WAI

25、T riseedge clock = 1;-if (clockevent and clock=1) then-WAIT UNTIL rising_edge(clock);-count = 1;-WAIT UNTIL (clockEVENT AND clock = 1);-WAIT UNTIL clock = 1;-if (clockevent and clock=1)then-WAIT UNTIL rising_edge(clock);-count = 2;-end if;-end if;-end if;- END PROCESS;END counter;九計(jì)數(shù)器library ieee;us

26、e ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;ENTITY ninecout ISPORT(clk,reset,enable : IN std_logic; count : OUT std_logic_vector(3 downto 0);END ninecout;ARCHITECTURE counter OF ninecout ISSIGNAL count_int:std_logic_vector(0 to 3);BEGINPROCESS(clk,reset)BEGINWAIT UNTIL rising_edge(clk)

27、;IF reset = 1 THENcount_int 0);ELSIF enable = 1 THENIF(count_int=1000) THENcount_int=0000;ELSEcount_int = count_int 1;-ELSE- NULL ;-IF (count_int=1001) THEN-count_int=0000;END IF;END IF;END PROCESS;count = count_int;- IF (reset=0) then-q=0000;-ELSIF(clkevent and clk=1) THEN-q=q 1;-IF (q=1001) then-q

28、=0000;-END IF;-IF (reset=1)THEN-q=00;-ELSIF-wait until (clkevent and clk=1);-WAIT UNTIL (clkEVENT AND clk = 1);-WAIT UNTIL (clockEVENT AND clock = 1);- q=q 1;-end if;-count=q;- WAIT UNTIL clock = 1;-if (clockevent and clock=1)then-WAIT UNTIL rising_edge(clock);-clockevent and clock=1;-count = 0;-WAI

29、T UNTIL (clockEVENT AND clock = 1);-WAIT riseedge clock = 1;-if (clockevent and clock=1) then-WAIT UNTIL rising_edge(clock);-count = 1;-WAIT UNTIL (clockEVENT AND clock = 1);-WAIT UNTIL clock = 1;-if (clockevent and clock=1)then-WAIT UNTIL rising_edge(clock);-count = 2;-end if;-end if;-end if;- END

30、PROCESS;END counter;八計(jì)數(shù)器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;ENTITY eightcout ISPORT(clk,reset,enable : IN std_logic; count : OUT std_logic_vector(2 downto 0);END eightcout;ARCHITECTURE counter OF eightcout ISSIGNAL count_int:std_logic_vector(0 to 2);BEGINPROCESS(

31、clk,reset)BEGINWAIT UNTIL rising_edge(clk);IF reset = 1 THENcount_int 0);ELSIF enable = 1 THENIF(count_int=111) THENcount_int=000;ELSEcount_int = count_int 1;-ELSE- NULL ;-IF (count_int=1001) THEN-count_int=0000;END IF;END IF;END PROCESS;count = count_int;- IF (reset=0) then-q=0000;-ELSIF(clkevent a

32、nd clk=1) THEN-q=q 1;-IF (q=1001) then-q=0000;-END IF;-IF (reset=1)THEN-q=00;-ELSIF-wait until (clkevent and clk=1);-WAIT UNTIL (clkEVENT AND clk = 1);-WAIT UNTIL (clockEVENT AND clock = 1);- q=q 1;-end if;-count=q;- WAIT UNTIL clock = 1;-if (clockevent and clock=1)then-WAIT UNTIL rising_edge(clock)

33、;-clockevent and clock=1;-count = 0;-WAIT UNTIL (clockEVENT AND clock = 1);-WAIT riseedge clock = 1;-if (clockevent and clock=1) then-WAIT UNTIL rising_edge(clock);-count = 1;-WAIT UNTIL (clockEVENT AND clock = 1);-WAIT UNTIL clock = 1;-if (clockevent and clock=1)then-WAIT UNTIL rising_edge(clock);-

34、count = 2;-end if;-end if;-end if;- END PROCESS;END counter;六計(jì)數(shù)器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;ENTITY sixcout ISPORT(clk,reset,enable : IN std_logic; count : OUT std_logic_vector(2 downto 0);END sixcout;ARCHITECTURE counter OF sixcout ISSIGNAL count_int:std_

35、logic_vector(0 to 2);BEGINPROCESS(clk,reset)BEGINWAIT UNTIL rising_edge(clk);IF reset = 1 THENcount_int 0);ELSIF enable = 1 THENIF(count_int=101) THENcount_int=000;ELSEcount_int = count_int 1;-ELSE- NULL ;-IF (count_int=1001) THEN-count_int=0000;END IF;END IF;END PROCESS;count = count_int;- IF (rese

36、t=0) then-q=0000;-ELSIF(clkevent and clk=1) THEN-q=q 1;-IF (q=1001) then-q=0000;-END IF;-IF (reset=1)THEN-q=00;-ELSIF-wait until (clkevent and clk=1);-WAIT UNTIL (clkEVENT AND clk = 1);-WAIT UNTIL (clockEVENT AND clock = 1);- q=q 1;-end if;-count=q;- WAIT UNTIL clock = 1;-if (clockevent and clock=1)

37、then-WAIT UNTIL rising_edge(clock);-clockevent and clock=1;-count = 0;-WAIT UNTIL (clockEVENT AND clock = 1);-WAIT riseedge clock = 1;-if (clockevent and clock=1) then-WAIT UNTIL rising_edge(clock);-count = 1;-WAIT UNTIL (clockEVENT AND clock = 1);-WAIT UNTIL clock = 1;-if (clockevent and clock=1)then-WAIT UNTIL rising_edge(clock);-count = 2;-end if;-end if;-end if;- END PROCESS;END counter

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