1、Flip-flopsChapter4nSN74xx1634-bit binaryParallel load capabilityActive low clearnLD : presetnCLR : clearnENP& ENT : input enable signal that control countingnRCO : carry-out(0-1)CLR A B C DENPENTCLKLD QA QB QC QDRCOA:LSB01111x0111xx0 x1xxx01xaxxxxbxxxxcxxxxdxxx0a0b0c0dRemains sameCount upCLK CLR

2、 LD ENP&ENT A B C D QA QB QC QDxx110CLR A B C DENPENTCLKLD QA QB QC QDRCOA:LSBnModulo-16 counternModulo-N counterN16N divided by 16 is 0.01111x0111xx0 x1xxx01xaxxxxbxxxxcxxxxdxxx0a0b0c0dRemains sameCount upCLK CLR LD ENP&ENT A B C D QA QB QC QDxx1CLR A B C DENPENTCLKLD QA QB QC QDRCOxnStep1

3、: 74ls163 modulo-10 counter0-9nStep2: 74ls163 modulo-6 counter0-5nStep3: connect two parts1CLR A B C DENPENTCLKLD QA QB QC QDRCO1CLR A B C DENPENTCLKLD QA QB QC QDRCOThe modulo-6 counter count up every 10 clock pulse which is presented to modulo-10.The active clock pulse is positive edge.The modulo-

4、10 counter nCLR=(QDQA)nThe CLR of modulo-10 goes from 1 to 0 at 9th positive edge, and goes from 0 to 1 at 10th clock pulse. In a word, the CLR of modulo-10 would generate a positive edge every 10 clock pulse.1CLR A B C DENPENTCLKLD QA QB QC QDRCO1CLR A B C DENPENTCLKLD QA QB QC QDRCOnStep1 : 1st 74

5、ls163 as modulo-10 counter (Low order)0906nStep2: 2nd 74ls163 as modulo-6 counter (High order)05nStep3: connect two parts1CLR A B C DENPENTCLKLD QA QB QC QDRCO1CLR A B C DENPENTCLKLD QA QB QC QDRCOThe modulo-10 counter would clear data either every 10 clock pulse or when the output of 1st 74ls163 me

6、ets 6 and the output of 2nd 74ls163 meets 5 .CLRmodulo-10=0 n1st (QDQCQBQA=1001) n 2nd (QDQCQBQA=0101) and 1st(QDQCQBQA=0110)CLRmodulo-10=0 n1st (QDQCQBQA=1001) n 2nd (QDQCQBQA=0101) and 1st(QDQCQBQA=0110)CLRmodulo-10=0nQ1AQ1B+ (Q2AQ2C) (Q1BQ1C)= 1CLRmodulo-10=(Q1AQ1B+ (Q2AQ2C) (Q1BQ1C) =(Q1AQ1B) (Q2AQ2C) +(Q1BQ1C) The modulo-6 counter would clear data when the output of 1st 74ls163 meets 6 and the output of 2nd 74ls163 meets 5 .CLRmodulo-6 =0 2nd(QDQCQBQA=0101 )and 1st(QDQCQBQA=0110)CLRmodulo-6=(Q2AQ2C)