1、EDA實(shí)驗(yàn)五 用狀態(tài)圖輸入法實(shí)現(xiàn)序列檢測(cè)器一、實(shí)驗(yàn)?zāi)康模毫私庑蛄袡z測(cè)器的基本原理，Mealy型和Moore型狀態(tài)機(jī)的基本原理，掌握狀態(tài)圖輸入法實(shí)現(xiàn)序列檢測(cè)器的方法，并進(jìn)行分析和仿真驗(yàn)證。二、實(shí)驗(yàn)內(nèi)容：本實(shí)驗(yàn)內(nèi)容是：用狀態(tài)圖輸入法設(shè)計(jì)一個(gè)序列檢測(cè)器，若檢測(cè)器收到一組碼流1110010則輸出為1，否則輸出為0。三、實(shí)驗(yàn)方法：實(shí)驗(yàn)方法：采用基于FPGA進(jìn)行數(shù)字邏輯電路設(shè)計(jì)的方法。采用的軟件工具是QuartusII軟件仿真平臺(tái)，采用的硬件平臺(tái)是Altera EPF10K20TI144_4的FPGA試驗(yàn)箱。實(shí)驗(yàn)步驟：1、繪制狀態(tài)圖。打開(kāi)QuartusII軟件平臺(tái)，建立工程文件夾，工程文件夾名稱(chēng)為exp_

2、detect3。然后點(diǎn)擊File中的New建立一個(gè)狀態(tài)圖文件（用State Machine File命令），然后設(shè)置并生成狀態(tài)圖。2、按照實(shí)驗(yàn)箱上FPGA的芯片名更改編程芯片的設(shè)置。操作是點(diǎn)擊Assign/Device,選取芯片的類(lèi)型。3、編譯與調(diào)試。確定狀態(tài)圖文件為當(dāng)前工程文件，點(diǎn)擊Complier進(jìn)行文件編譯。編譯結(jié)果有錯(cuò)誤或警告，則將要調(diào)試修改直至文件編譯成功。4、波形仿真及驗(yàn)證。在編譯成功后，點(diǎn)擊Waveform開(kāi)始設(shè)計(jì)波形。點(diǎn)擊“insert the node”,按照程序所述引腳,任意設(shè)置各輸入節(jié)點(diǎn)的輸入波形點(diǎn)擊保存按鈕保存。5、FPGA芯片編程及驗(yàn)證，應(yīng)記錄實(shí)驗(yàn)結(jié)果進(jìn)行分析。四、實(shí)

3、驗(yàn)過(guò)程：用狀態(tài)圖輸入法實(shí)現(xiàn)序列檢測(cè)器：1、建立工程文件，工程文件夾的名稱(chēng)為exp_detect3，工程名和頂層實(shí)體名稱(chēng)為exp_detect3。工程建立過(guò)程中平臺(tái)設(shè)置設(shè)置如下圖所示：2、工程建好后，即進(jìn)行狀態(tài)圖的輸入。具體過(guò)程如下：選擇菜單File->New->State Machine File命令，打開(kāi)State Machine Editor窗口，如下圖所示：然后選擇Tools->State Machine Wizard 命令，彈出如下所示狀態(tài)機(jī)創(chuàng)建向?qū)?duì)話框。在該對(duì)話框中選擇Create a new state machine design 單選按鈕，點(diǎn)擊OK按鈕進(jìn)入下

4、一個(gè)頁(yè)面，如下所示：然后在下一個(gè)對(duì)話框中選擇復(fù)位Reset信號(hào)為異步Asynchronous，高電平有效，輸出端無(wú)寄存器。單擊Next按鈕進(jìn)入下一個(gè)頁(yè)面。在狀態(tài)轉(zhuǎn)換對(duì)話框中設(shè)置狀態(tài)轉(zhuǎn)換。States欄中輸入狀態(tài)名稱(chēng)s0s6。Input ports欄中輸入時(shí)鐘信號(hào)clock、復(fù)位信號(hào)reset以及串行數(shù)據(jù)輸入信號(hào)din。State transitions 欄中依據(jù)書(shū)中狀態(tài)圖指定的狀態(tài)轉(zhuǎn)換，設(shè)置完成后點(diǎn)擊Next按鈕，進(jìn)入下一頁(yè)面：s0->s1 dins0->s0 dins1->s2 dins1->s0 dins2->s3 dins2->s0 dins3->

5、;s4 dins3->s3 dins4->s5 dins4->s1 dins5->s0 dins5->s6 dins6->s0 dins6->s2 din在output ports欄Output Port Name 列中輸入z，Output State 狀態(tài)設(shè)為Current clock cycle 。Action condition 欄設(shè)為s6狀態(tài)且Additional Conditions為“din”成立時(shí)信號(hào)，z輸出為1 。設(shè)置完成后單擊next按鈕進(jìn)入下一個(gè)頁(yè)面：在下圖對(duì)話框中顯示狀態(tài)機(jī)的設(shè)置情況。單擊Finish按鈕，關(guān)閉狀態(tài)機(jī)向?qū)?，生成所?/p>

6、的狀態(tài)機(jī)。布局適當(dāng)調(diào)整，得到所需的狀態(tài)圖，狀態(tài)圖如下圖所示：生成并調(diào)整后的狀態(tài)圖：3、保存該設(shè)計(jì)文件為exp_detect3.smf，并添加到工程文件夾。4、選擇菜單Tools->Gennrate HDL File 命令，打開(kāi)Gennrate HDL File對(duì)話框，如下圖所示，從中選擇VHDL單選項(xiàng)，單擊OK按鈕，分析成功后則自動(dòng)生成exp_detect3.vhd。生成的VHDL代碼如下：LIBRARY ieee;USE ieee.std_logic_1164.all;ENTITY exp_detect3 IS PORT ( clock : IN STD_LOGIC; reset :

7、IN STD_LOGIC := '0' din : IN STD_LOGIC := '0' z : OUT STD_LOGIC );END exp_detect3;ARCHITECTURE BEHAVIOR OF exp_detect3 IS TYPE type_fstate IS (s0,s1,s2,s3,s4,s5,s6); SIGNAL fstate : type_fstate; SIGNAL reg_fstate : type_fstate;BEGIN PROCESS (clock,reset,reg_fstate) BEGIN IF (reset=&#

8、39;1') THEN fstate <= s0; ELSIF (clock='1' AND clock'event) THEN fstate <= reg_fstate; END IF; END PROCESS; PROCESS (fstate,din) BEGIN z <= '0' CASE fstate IS WHEN s0 => IF (din = '1') THEN reg_fstate <= s1; ELSIF (NOT(din = '1') THEN reg_fstate

9、 <= s0; - Inserting 'else' block to prevent latch inference ELSE reg_fstate <= s0; END IF; WHEN s1 => IF (din = '1') THEN reg_fstate <= s2; ELSIF (NOT(din = '1') THEN reg_fstate <= s0; - Inserting 'else' block to prevent latch inference ELSE reg_fstate

10、<= s1; END IF; WHEN s2 => IF (din = '1') THEN reg_fstate <= s3; ELSIF (NOT(din = '1') THEN reg_fstate <= s0; - Inserting 'else' block to prevent latch inference ELSE reg_fstate <= s2; END IF; WHEN s3 => IF (din = '1') THEN reg_fstate <= s3; ELSIF

11、(NOT(din = '1') THEN reg_fstate <= s4; - Inserting 'else' block to prevent latch inference ELSE reg_fstate <= s3; END IF; WHEN s4 => IF (din = '1') THEN reg_fstate <= s1; ELSIF (NOT(din = '1') THEN reg_fstate <= s5; - Inserting 'else' block to p

12、revent latch inference ELSE reg_fstate <= s4; END IF; WHEN s5 => IF (din = '1') THEN reg_fstate <= s6; ELSIF (NOT(din = '1') THEN reg_fstate <= s0; - Inserting 'else' block to prevent latch inference ELSE reg_fstate <= s5; END IF; WHEN s6 => IF (din = '1

13、') THEN reg_fstate <= s2; ELSIF (NOT(din = '1') THEN reg_fstate <= s0; - Inserting 'else' block to prevent latch inference ELSE reg_fstate <= s6; END IF; IF (NOT(din = '1') THEN z <= '1' - Inserting 'else' block to prevent latch inference ELSE

14、z <= '0' END IF; WHEN OTHERS => z <= 'X' report "Reach undefined state" END CASE; END PROCESS;END BEHAVIOR;5、把exp_detect3.vhd作為設(shè)計(jì)源文件用于后序?qū)嶒?yàn)驗(yàn)證。代碼生成后進(jìn)行編譯（可在此時(shí)設(shè)置引腳等等）6、現(xiàn)在可用RTL viewer 查看電路，如下圖所示，狀態(tài)圖可選擇Tools->Netlist viewers->State Machine Viewer命令查看：7、下面進(jìn)行功能仿真：波形仿真過(guò)程。點(diǎn)擊file->new,選擇Vector Waveform File,新建一個(gè)波形仿真文件，然后在空白處點(diǎn)擊右鍵，選擇“Insert Node or Bus”,出現(xiàn)一個(gè)對(duì)話框，進(jìn)行添加節(jié)點(diǎn)，然后輸入時(shí)鐘激勵(lì)信號(hào)，并進(jìn)行參數(shù)設(shè)置，兩個(gè)重要的參數(shù):End time結(jié)束時(shí)間和Grid size網(wǎng)格大小。點(diǎn)擊Edit->Value->Clock,出現(xiàn)一個(gè)對(duì)話框設(shè)置時(shí)鐘激勵(lì)周期，相位以及其他參數(shù)，點(diǎn)擊OK，顯示波形圖如下：接著保存波形文件，然后進(jìn)行仿真。在仿真之前要先生成功能仿真表，首先要先設(shè)置仿真模式。然后點(diǎn)擊菜單項(xiàng)Process