1、精選優(yōu)質(zhì)文檔-傾情為你奉上 基于FPGA的數(shù)字系統(tǒng)設(shè)計(jì) 大作業(yè) 學(xué)號(hào)： 姓名： 邢武天 班級(jí)： 題目一：設(shè)計(jì)Parwan 的control section 內(nèi)部狀態(tài)機(jī)s1s2.s9,并給出功能仿真？ 題目二：利用分層結(jié)構(gòu)設(shè)計(jì)ParwanCPU,并給出功能仿真? （利用在實(shí)驗(yàn)課中所給出的TESTBENCH）實(shí)驗(yàn)原理圖Control Section Structure：s1s9（如下圖所示）Inputs and outputs of PARWAN control sections: Applied to, categories, signal name, functions 實(shí)驗(yàn)過(guò)程1.1 創(chuàng)建工

2、程（1）打開(kāi)ISE13.x軟件，選擇File->New Project在彈出的對(duì)話框中輸入工程名和路徑。（2）單擊下一步選擇所使用的芯片。Spartan3E開(kāi)發(fā)板的芯片型號(hào)為Spartan3E XC3S500E芯片，F(xiàn)G320封裝。（3）單擊Next，進(jìn)入工程信息頁(yè)面，確認(rèn)無(wú)誤后，點(diǎn)擊Finish完成工程的創(chuàng)建。1.2 測(cè)試文件(1) 選擇菜單欄中的Project->New Source。(2) 在Select Source Type窗口中，選擇左側(cè)的VHDL Test Bench,在右側(cè)File Name欄中輸入文件名par_control_unit_tb(3) 單擊Next按鈕

3、，選擇關(guān)聯(lián)文件。1.3 實(shí)驗(yàn)截圖實(shí)驗(yàn)代碼在實(shí)現(xiàn)過(guò)程中，除了定義CPU的信號(hào)接口外，還設(shè)置了一個(gè)輸出類(lèi)型的接口，名字叫present_state_value,主要是用來(lái)在調(diào)試或仿真的過(guò)程中輸出CPU所處的狀態(tài)，便于調(diào)試分析。整個(gè)狀態(tài)機(jī)的實(shí)現(xiàn)過(guò)程主要使用了case IS when 邏輯結(jié)構(gòu)。用了present_state 和next_state兩個(gè)狀態(tài)變量。詳細(xì)的實(shí)現(xiàn)代碼如下所示：LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE work.synthesis_utilities.ALL; - ENTITY par_control_unit IS PORT

4、 (clk : IN std_logic; - register control signals: load_ac, zero_ac, load_ir, increment_pc, load_page_pc, load_offset_pc, reset_pc, load_page_mar, load_offset_mar, load_sr, cm_carry_sr, - bus connection control signals: pc_on_mar_page_bus, ir_on_mar_page_bus, pc_on_mar_offset_bus, dbus_on_mar_offset_

5、bus, pc_offset_on_dbus, obus_on_dbus, databus_on_dbus, mar_on_adbus, dbus_on_databus, - logic unit function control outputs: arith_shift_left, arith_shift_right : OUT std_logic; alu_and,alu_not,alu_a,alu_add,alu_b,alu_sub: out std_logic; - inputs from the data section: ir_lines : IN std_logic_vector

6、 (7 DOWNTO 0); status : IN std_logic_vector (3 DOWNTO 0); - memory control and other external signals: read_mem, write_mem : OUT std_logic; interrupt : IN std_logic; -test present_state_value: out std_logic_vector (3 DOWNTO 0) ); END par_control_unit; - ARCHITECTURE dataflow_synthesizable OF par_con

7、trol_unit IS TYPE cpu_states IS (s1,s2,s3,s4,s5,s6,s7,s8,s9); SIGNAL present_state, next_state : cpu_states; SIGNAL next_state_value: std_logic_vector (3 DOWNTO 0); BEGIN clocking : PROCESS (clk, interrupt) BEGIN IF (interrupt = '1') THEN present_state <= s1; present_state_value <=&quo

8、t;0001" ELSIF clk'EVENT AND clk = '0' THEN present_state <= next_state; present_state_value <=next_state_value; END IF; END PROCESS clocking; - sequencing : PROCESS ( present_state, ir_lines, status, interrupt) BEGIN load_ac <= '0' zero_ac <= '0' load_ir

9、<= '0' increment_pc <= '0' load_page_pc <= '0' load_offset_pc <= '0' reset_pc <= '0' load_page_mar <= '0' load_offset_mar <= '0' load_sr <= '0' cm_carry_sr <= '0' - bus connection control signals: pc_o

10、n_mar_page_bus <= '0' ir_on_mar_page_bus <= '0' pc_on_mar_offset_bus <= '0' dbus_on_mar_offset_bus <= '0' pc_offset_on_dbus <= '0' obus_on_dbus <= '0' databus_on_dbus <= '0' mar_on_adbus <= '0' dbus_on_databus &l

11、t;= '0' - logic unit function control outputs: arith_shift_left <= '0' arith_shift_right <= '0' alu_and <='0'alu_not <='0'alu_a <='0'alu_add <='0'alu_b <='0'alu_sub <='0' - memory control and other extern

12、al signals: read_mem <= '0' write_mem <= '0' CASE present_state IS WHEN s1 => -1 IF (interrupt = '1') THEN reset_pc <= '1' next_state <= s1; next_state_value <="0001" ELSE pc_on_mar_page_bus <= '1' pc_on_mar_offset_bus <= '

13、;1' load_page_mar <= '1' load_offset_mar <= '1' next_state <= s2; next_state_value <="0010" END IF; WHEN s2 => -2 - read memory into ir mar_on_adbus <= '1' read_mem <= '1' databus_on_dbus <= '1' alu_a <= '1' loa

14、d_ir <= '1' increment_pc <= '1' next_state <= s3; next_state_value <="0011" WHEN s3 => -3 pc_on_mar_page_bus <= '1' pc_on_mar_offset_bus <= '1' load_page_mar <= '1' load_offset_mar <= '1' IF (ir_lines (7 DOWNTO 4) /

15、= "1110") THEN next_state <= s4; next_state_value <="0100" ELSE CASE ir_lines (3 DOWNTO 0) IS WHEN "0001" => -cla zero_ac <= '1' load_ac <= '1' WHEN "0100" => -cmc cm_carry_sr <= '1' WHEN "1000" => -asl

16、 alu_b <= '1' arith_shift_left <= '1' load_sr <= '1' load_ac <= '1' WHEN "1001" => -asr alu_b <= '1' arith_shift_right <= '1' load_sr <= '1' load_ac <= '1' WHEN OTHERS => NULL; END CASE; next_stat

17、e <= s2; next_state_value <="0010" END IF; WHEN s4 => -4 - read memory into mar offset mar_on_adbus <= '1' read_mem <= '1' databus_on_dbus <= '1' dbus_on_mar_offset_bus <= '1' load_offset_mar <= '1' IF ( ir_lines (7 DOWNTO 6)

18、/= "11" ) THEN ir_on_mar_page_bus <= '1' load_page_mar <= '1' IF ( ir_lines (4) = '1' ) THEN next_state <= s5; next_state_value <="0101"ELSE next_state <= s6; next_state_value <="0110" END IF; ELSE -jsr or bra, do not alter mar

19、- page IF ( ir_lines (5) = '0' ) THEN - jsr next_state <= s7; next_state_value <="0111" ELSE next_state <= s9; next_state_value <="1001" END IF; END IF; increment_pc <= '1' WHEN s5 => -5 - read actual operand from memory into mar - offset mar_on_

20、adbus <= '1' read_mem <= '1' databus_on_dbus <= '1' dbus_on_mar_offset_bus <= '1' load_offset_mar <= '1' next_state <= s6; next_state_value <="0110" WHEN s6 => -6 IF ( ir_lines (7 DOWNTO 5) = "100" ) THEN -jmp load_p

21、age_pc <= '1' load_offset_pc <= '1' next_state <= s2; next_state_value <="0010" ELSIF ( ir_lines (7 DOWNTO 5) = "101" ) THEN - mar on adbus, ac on databus, write -to memory mar_on_adbus <= '1' alu_b<= '1' obus_on_dbus <= '1

22、' dbus_on_databus <= '1' write_mem <= '1' next_state <= s1; next_state_value <="0001" ELSIF ( ir_lines (7) = '0' ) THEN - -lda, and, add, sub - mar on adbus, read memory for -operand, perform operation mar_on_adbus <= '1' read_mem <= &#

23、39;1' databus_on_dbus <= '1' IF ( ir_lines (6) = '0' ) THEN- lda, and IF ( ir_lines (5) = '0' )THEN - lda alu_a<= '1' ELSE - and alu_and<= '1' END IF; ELSE - add, sub IF ( ir_lines (5) = '0' ) THEN - add alu_add<= '1' ELSE - sub

24、 alu_sub<= '1' END IF; END IF; load_sr <= '1' load_ac <= '1' next_state <= s1; next_state_value <="0001" END IF; WHEN s7 => -7 - write pc offset to top of subroutine mar_on_adbus <= '1' pc_offset_on_dbus <= '1' dbus_on_databus

25、 <= '1' write_mem <= '1' load_offset_pc <= '1' next_state <= s8; next_state_value <="1000" WHEN s8 => -8 increment_pc <= '1' next_state <= s1; next_state_value <="0001" WHEN s9 => -9 IF ( all_or (status AND ir_lines (3

26、 DOWNTO 0) = '1') THEN load_offset_pc <= '1' END IF; next_state <= s1; next_state_value <="0001" 實(shí)驗(yàn)原理實(shí)驗(yàn)過(guò)程2.1 創(chuàng)建工程（1）打開(kāi)ISE13.x軟件，選擇File->New Project在彈出的對(duì)話框中輸入工程名和路徑。（2）單擊下一步選擇所使用的芯片。Spartan3E開(kāi)發(fā)板的芯片型號(hào)為Spartan3E XC3S500E芯片，F(xiàn)G320封裝。（3）單擊Next，進(jìn)入工程信息頁(yè)面，確認(rèn)無(wú)誤后，點(diǎn)擊Finish完

27、成工程的創(chuàng)建。2.2 設(shè)計(jì)輸入選擇Project->Add copy of source，將實(shí)驗(yàn)的源代碼添加到工程中。2.3 綜合實(shí)現(xiàn)（1） 編寫(xiě)匯編測(cè)試代碼（2）用文本編輯器打開(kāi)實(shí)驗(yàn)源代碼中的simple.asm文件。（3）將測(cè)試代碼轉(zhuǎn)換為內(nèi)存文件（4）編譯并執(zhí)行程序2.4 設(shè)計(jì)仿真2.5 結(jié)果截圖編寫(xiě)testbench代碼對(duì)以上的狀態(tài)機(jī)進(jìn)行功能仿真。Testbench的核心代碼如下： stim_proc: process begin - hold reset state for 100 ns. wait for 10 ns;ir_lines <= "" -SUB loc wait for clk_period*10;ir_lines <= "" -JMP loc wait for clk_period*10;ir_lines <= "" -STA loc wait fo