1、文檔來(lái)源為：從網(wǎng)絡(luò)收集整理.word版本可編輯.歡迎下載支持計(jì)算機(jī)組成原理課程設(shè)計(jì)報(bào)告題目：設(shè)計(jì)一臺(tái)嵌入式CISC模型機(jī)院系：計(jì)算機(jī)科學(xué)與工程學(xué)院專(zhuān)業(yè)：網(wǎng)絡(luò)工程姓名：麥健豪學(xué)號(hào)：15、課程設(shè)計(jì)的題目和內(nèi)容采用定長(zhǎng)CPU周期、聯(lián)合控制方式，并運(yùn)行能完成一定功能的機(jī)器語(yǔ)言源程序進(jìn)行驗(yàn)證，機(jī)器語(yǔ)言源程序功能如下：輸入5個(gè)有符號(hào)整數(shù)（8位二進(jìn)制補(bǔ)碼表示），求最大負(fù)數(shù)的絕對(duì)值并輸出顯示。說(shuō)明：5個(gè)有符號(hào)數(shù)從外部輸入；一定要使用符號(hào)標(biāo)志位（比如說(shuō)SF）,并且要使用為負(fù)的時(shí)候轉(zhuǎn)移（比如JS）或不為負(fù)的時(shí)候轉(zhuǎn)移（比如JNS）指令；采用單數(shù)據(jù)總線結(jié)構(gòu)的運(yùn)算器。系統(tǒng)設(shè)計(jì)2.1系統(tǒng)的總體設(shè)計(jì)外部時(shí)鐘復(fù)位信號(hào)外部時(shí)鐘

2、復(fù)位信號(hào)2.2設(shè)計(jì)控制器的邏輯結(jié)構(gòu)框圖指令寄存器IR指令寄存器IR說(shuō)明：在T4內(nèi)形成微指令的微地址，并訪問(wèn)控制存儲(chǔ)器，在T2的上邊沿到來(lái)時(shí),將讀出的微指令打入微指令寄存器，即圖中的微命令寄存器和微地址寄存器。2.3設(shè)計(jì)機(jī)器指令和指令系統(tǒng)指令對(duì)象功能機(jī)器指令Mov1XX,RDDATA-RD0011DATATESTXX,RDAC鎖存FS0100JNSXXXXADDR-PC0101ADDRINCXX,RDRD+1-RD0110INXX,RDSW-RD0111CMPRS,RDRS-RD鎖存FS1001MOV2RS,RDRS-RD1010JMPXXXXADDR-PC1011ADDRNEGXX,RD(0-

3、RD)-RD1100OUTRS,XXRS-LED1101以下是對(duì)Rs,Rd的規(guī)定:Rs或Rd選定的寄存器00R001R110R2模型機(jī)規(guī)定數(shù)據(jù)的表示采用定點(diǎn)整數(shù)補(bǔ)碼表示，單字長(zhǎng)為8位,其格式如下：76543210符號(hào)位尾數(shù)2.4設(shè)計(jì)時(shí)序產(chǎn)生器與CLR、Q之間的關(guān)系圖CLRIQJULJUTOCo1-5hzT1|iT2j|T3iIu1Ib個(gè)CPU周期2.5設(shè)計(jì)微程序流程圖X1OV1X1OV1lETIKL030405P:-rAFPC-1OEROMBtrsSF=1貳6MB口P3ARPC-1AJ+1-5-HLS2020SF=Of12BUZjtK：30mmM11FROU00020006ns注門(mén).5V.-3

4、-EU5E匸A逕CMPRJJHUSAC-DRMOV2代EH3MPPCDC-1ixHen&OUT0D刁T-A-l-19良644鄧1BUEFC4/ISj_h-*BUED2.6設(shè)計(jì)操作控制器單元2.6設(shè)計(jì)操作控制器單元(1)設(shè)計(jì)微指令格式與微指令代碼表CISC模型機(jī)系統(tǒng)使用的微指令采用全水平型微指令，字長(zhǎng)為位，P字段為2位，后繼微地址為6位，其格式如下：25位，其中微命令字段為1727272625212322212019181716151412111076513210RAMBnCSLOADLDPCLD跟LOIRLDRiRDBRSESi30ALUELDACLDDRHR0CS_ISffBLEDBLDFR

5、FlP2后繼微地址設(shè)計(jì)的具體指令為:16進(jìn)制微地址LOADLDPCLDARLDIRLDRiRDBRBSS0ALUBLDACLDDRWR/CSSWBL/EDBLDFRP1P2后繼微地址0000000010000000100200001010100000000300001110000011100400010010000011110500010110011000000600011010000100100700011110000000000900100110000101010A0010101000000000OB00101110000110000C00110010000110010D001101000

6、00000000E00111010000000000F0011111100000000120100101000000000150101011000010110160101101100000000180110000000000000190110011000000000301100001000000000201000000000000000（2）設(shè)計(jì)地址轉(zhuǎn)移邏輯電路地址轉(zhuǎn)移邏輯電路是根據(jù)微程序流程圖的棱形框部分及多個(gè)分支微地址，利用微地址寄存器的異步置1端，實(shí)現(xiàn)微地址的多路轉(zhuǎn)移的。由于是采用邏輯電路來(lái)實(shí)現(xiàn)的，故稱(chēng)之為地址轉(zhuǎn)移邏輯電路。在微地址流程圖中，P（1）（高電平有效）測(cè)試時(shí)，根據(jù)指令的操作1

7、714強(qiáng)制修改后繼地址的低四位；在P（2）（高電平有效）時(shí)，根據(jù)借位標(biāo)志FS進(jìn)行2路分支，并且都在T4內(nèi)形成后繼微指令的微地址。SE5=(N0TFS)ANDP(2)ANDT4SE4=(I7ANDP(2)ANDT4SE3=(I6ANDP(2)ANDT4SE2=(I5ANDP(2)ANDT4SE1=(I4ANDP(2)ANDT42.7設(shè)計(jì)單元頂層電路2.8編寫(xiě)匯編語(yǔ)言源程序算法：R0存入一個(gè)整數(shù)-4，作為五次輸入循環(huán)使用；R1用于存儲(chǔ)輸入的整數(shù)；R3用于存入最后的結(jié)果，并預(yù)存一個(gè)最小負(fù)數(shù)-128.隨后如下Mov1R0,-5將立即數(shù)-4-R0MOV1R2,-128將立即數(shù)-128-R2L1TESTR

8、O測(cè)試R0，鎖存SFJNSL2非負(fù)，即SF=0，跳轉(zhuǎn)L2INCR0R0+1INR1輸入一個(gè)整數(shù)，并存入R1TESTR1測(cè)試R1JNSL1非負(fù)則跳轉(zhuǎn)L1CMPR2,R1比較R2,R1的大小，鎖存SFJNSL1非負(fù)則跳轉(zhuǎn)L1MOV2R1,R2將R1的內(nèi)容存入R2JMPL1跳轉(zhuǎn)L1L2NEGR2對(duì)R2求補(bǔ)OUTR2輸出結(jié)果2.9機(jī)器語(yǔ)言源程序指令地址地址16進(jìn)制機(jī)器指令十六進(jìn)制備注Mov1R0,-5000000000000110000300000000101FBMOV1R2,-128000000100200110010320000001103FFL1TESTRO0000010004010000004

9、0JNSL20000010105010100005000000110060001001011INCRO00000111070110000060INR100001000080111000171TESTR100001001090100000141JNSL1000010100A0101000050000010110B0000010004CMPR2,R1000011000C99JNSL1000011010D0101000050000011100E0000010004MOV2R1,R2000011110FA6JMPL10001000010B000010001110000010004L2NEGR20001

10、001012C2OUTR20001001113D8CISC模型機(jī)的單元電路3.1ALU單元aiLuR7B7.三j.3BcilBCDOUT7.0SFS-C3S1S0功能00AC-DR,鎖存FS01AC鎖存FS10自加111求補(bǔ)LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_ARITH.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYALUISPORT(A:INSTD_L0GIC_VECT0R(7DOWNTO0);B:INSTD_LOGIC_VECTOR(7DOWNTO0);S1,S0:INSTD_

11、LOGIC;BCDOUT:OUTSTD_LOGIC_VECTOR(7DOWNTO0);SF:OUTSTD_LOGIC);ENDALU;ARCHITECTUREAOFALUISSIGNALAA,BB,TEMP:STD_LOGIC_VECTOR(7DOWNTO0);BEGINPROCESS(S1,SO)BEGINIF(S1=OANDS0=0)THENTEMP=A-B;SF=TEMP(7);BCDOUT=TEMP(7DOWNTO0);ELSIF(S1=0ANDS0=1)THENTEMP=A-0;SF=TEMP(7);BCDOUT=TEMP(7DOWNTO0);ELSIF(S1=1ANDS0=0)TH

12、ENTEMP=A+1;BCDOUT=TEMP(7DOWNTO0);ELSIF(S1=1ANDS0=1)THENTEMP=0-A;BCDOUT=TEMP(7DOWNTO0);ENDIF;ENDPROCESS;ENDA;3.2寄存器單元LS74LDFR上升沿有效。LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYLS74ISPORT(LDFR:INSTD_LOGIC;SF:INSTD_LOGIC;FS:OUTSTD_LOGIC);ENDLS74;ARCHITECTUREAOFLS74ISBEGINPROCESS(LDFR)BEGINIF(LDFREVENTA

13、NDLDFR=1)THENFS=SF;ENDIF;ENDPROCESS;ENDA;LS273LG272:DIr_-OJO-uJ.3=0而暫存寄存器與通用寄存器則是使用LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYLS273IS通用寄存器功能表RO1R1BR2BALUB功能1110輸出ALU0111輸出R01011輸出R11101輸出R2PORT(D:INSTD_LOGIC_VECTOR(7DOWNTO0);CLK:INSTD_LOGIC;O:OUTSTD_LOGIC_VECTOR(7DOWNTO0);ENDLS273;ARCHITECTUREAOFL

14、S273ISBEGINPROCESS(CLK)BEGINIF(CLKEVENTANDCLK=1)THENO=D;ENDIF;ENDPROCESS;ENDA;1:2分配器單元XIE-HIJ_E丁-MR-XIE-HIJ_E丁-MR-FEN2AQ輸入輸出WRLED_BX7.0W17.0W27.000XX7.0其他值XX7.0LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYFEN2ISPORT(X:INSTD_LOGIC_VECTOR(7DOWNTO0);WR,LED_B:INSTD_LOGIC;W1,W2:OUTSTD_LOGIC_VECTOR(7DOWNT

15、O0);ENDFEN2;ARCHITECTUREAOFFEN2ISBEGINPROCESS(LED_B,WR)BEGINIF(LED_B=OANDWR=O)THENW2=X;ELSEW1=X;ENDIF;ENDPROCESS;ENDA;3選1數(shù)據(jù)選擇器單元LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYMUX3ISPORT(ID:INSTD_LOGIC_VECTOR(7DOWNTO0);SW_B,CS:INSTD_LOGIC;N1,N2:INSTD_LOGIC_VECTOR(7DOWNTO0);EW:OUTSTD_LOGIC_VECTOR(7DOWNT

16、O0);ENDMUX3;ARCHITECTUREAOFMUX3ISBEGINPROCESS(SW_B,CS)BEGINIF(SW_B=O)THENEW=ID;ELSIF(CS=0)THENEW=N2;ELSEEW=N1;ENDIF;ENDPROCESS;ENDA;4選1數(shù)據(jù)選擇器單元HUX4XJ.IL7.xzr7.LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYMUX4ISPORT(C,D,E,F:INSTD_LOGIC;X1,X2,X3,X4:INSTD_L0GIC_VECT0R(7DOWNTO0);W:outSTD_LOGIC_VECTOR(7DO

17、WNTO0);ENDMUX4;ARCHITECTUREAOFMUX4ISSIGNALSEL:STD_LOGIC_VECTOR(3DOWNTO0);BEGINSEL=F&E&D&C;PROCESS(SEL)BEGINIF(SEL=1110)THEN-R0_outW=X1;ELSIF(SEL=1101)THEN-R1_outW=X2;ELSIF(SEL=1011)THEN-R2-outW=X3;ELSIF(SEL=0111)THEN-R3_outW=X4;ELSEnull;ENDIF;ENDPROCESS;ENDA;3.6程序計(jì)數(shù)器單元PcLIBRARYIEEE;USEIEEE.STD_LOGIC

18、_1164.ALL;USEIEEE.STD_LOGIC_ARITH.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYPCISPORT(load,LDPC,CLR:INSTD_LOGIC;D:INSTD_L0GIC_VECT0R(7DOWNTO0);O:OUTSTD_LOGIC_VECTOR(7DOWNTO0);ENDPC;ARCHITECTUREAOFPCISSIGNALQOUT:STD_LOGIC_VECTOR(7DOWNTO0);BEGINPROCESS(LDPC,CLR,load)BEGINIF(CLR=0)THENQOUT=OOOOOOOO;ELSIF

19、(LDPCEVENTANDLDPC=1)THENIF(load=0)THENQOUTPCELSEQOUT=QOUT+1;-PC+1ENDIF;ENDIF;ENDPROCESS;OADDRC?-0DOUTC?-Gcs20LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_ARITH.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYROM16ISPORT(DOUT:OUTSTD_L0GIC_VECT0R(7DOWNTO0);ADDR:INSTD_LOGIC_VECTOR(7DOWNTO0);CS:INS

20、TD_LOGIC);ENDROM16;ARCHITECTUREAOFROM16ISBEGINDOUT=OO11OOOOWHENADDR=OOOOOOOOANDCS=0ELSEWHENADDR=00000001ANDCS=0ELSE00110010WHENADDR=00000010ANDCS=0ELSEWHENADDR=00000011ANDCS=0ELSE01000000WHENADDR=00000100ANDCS=0ELSE01010000WHENADDR=00000101ANDCS=0ELSE00010010WHENADDR=00000110ANDCS=0ELSE01100000WHENA

21、DDR=00000111ANDCS=0ELSE01110001WHENADDR=00001000ANDCS=0ELSE01000001WHENADDR=00001001ANDCS=0ELSE01010000WHENADDR=00001010ANDCS=0ELSE00000100WHENADDR=00001011ANDCS=0ELSEWHENADDR=00001100ANDCS=0ELSE01010000WHENADDR=00001101ANDCS=0ELSE00000100WHENADDR=00001110ANDCS=0ELSEWHENADDR=00001111ANDCS=0ELSEWHENA

22、DDR=00010000ANDCS=0ELSE00000100WHENADDR=00010001ANDCS=0ELSEWHENADDR=00010010ANDCS=0ELSEWHENADDR=00010011ANDCS=0ELSE00000000;ENDA;3.9指令寄存器單元3.10時(shí)序產(chǎn)生器單元LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_ARITH.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYCOUNTERISPORT(Q,CLR:INSTD_LOGIC;T2,T3,T4:OUTST

23、D_LOGIC);ENDCOUNTER;ARCHITECTUREAOFCOUNTERISSIGNALX:STD_LOGIC_VECTOR(1DOWNTO0);BEGINPROCESS(Q,CLR)BEGINIF(CLR=0)THENT2=0;T3=0;T4=0;X=00;ELSIF(QEVENTANDQ=1)THENX=X+1;T2=(NOTX(1)ANDX(0);T3=X(1)AND(NOTX(0);T4=X(1)ANDX(0);ENDIF;ENDPROCESS;ENDA;3.11操作控制器單元nrom尸空巨冃士邑swuml地址轉(zhuǎn)移邏輯電路ADDRLIBRARYIEEE;USEIEEE.ST

24、D_LOGIC_1164.ALL;ENTITYADDRISPORT(I7,I6,I5,I4:INSTD_LOGIC;FS,T4,P1,P2:INSTD_LOGIC;SE6,SE5,SE4,SE3,SE2,SE1:OUTSTD_LOGIC);ENDADDR;ARCHITECTUREAOFADDRISBEGINSE6=1：SE5=N0T(FSANDP2ANDT4);SE4=NOT(I7ANDP1ANDT4);SE3=NOT(I6ANDP1ANDT4);SE2=NOT(I5ANDP1ANDT4);SE1=N0T(I4ANDP1ANDT4);ENDA;微地址寄存器LIBRARYIEEE;USEIEEE

25、.STD_LOGIC_1164.ALL;ENTITYMMMISPORT(SE:INSTD_LOGIC;T2:INSTD_LOGIC;D:INSTD_LOGIC;CLR:INSTD_LOGIC;UA:OUTSTD_LOGIC);ENDMMM;ARCHITECTUREAOFMMMISBEGINPROCESS(CLR,SE,T2)BEGINIF(CLR=0)THENUA=0：ELSIF(SE=O)THENUA=1;ELSIF(T2EVENTANDT2=1)THENUA=D;ENDIF;ENDPROCESS;ENDA;微地址轉(zhuǎn)換器F1LIBRARYIEEE;USEIEEE.STD_LOGIC_1164

26、.ALL;ENTITYF1ISPORT(UA5,UA4,UA3,UA2,UA1,UA0:INSTD_LOGIC;D:OUTSTD_LOGIC_VECTOR(5DOWNTO0);ENDF1;ARCHITECTUREAOFF1ISBEGIND(5)=UA5;D(4)=UA4;D(3)=UA3;D(2)=UA2;D(1)=UA1;D(0)DATAOUTDATAOUTDATAOUTDATAOUTDATAOUTDATAOUTDATAOUTDATAOUTDATAOUTDATAOUTDATAOUTDATAOUTDATAOUTDAWHEN001111=DATAOUTDAWHEN100000=DATAOUTDA

27、WHEN010010=DATAOUTDATAOUTDATAOUTDATAOUTDATAOUTDATAOUTDATAOUTDATAOUT=00;ENDCASE;UA(5DOWNTO0)=DATAOUT(5DOWNTO0);D(18DOWNTO0)=DATAOUT(24DOWNTO6);ENDPROCESS;ENDA;微命令寄存器LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_ARITH.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYMCOMMANDISPORT(T2,T3,T4,I3,I2,I1

28、,IO:INSTD_LOGIC;O:INSTD_LOGIC_VECTOR(18DOWNTO0);P1,P2,LOAD,LDPC,LDAR,LDIR,LDR0,LDR1,LDR2,R0_B,R1_B,R2_B,S1,S0,ALU_B,LDAC,LDDR,WR,CS,SW_B,LED_B,LDFR:OUTSTD_LOGIC);ENDMCOMMAND;ARCHITECTUREAOFMCOMMANDISSIGNALDATAOUT:STD_LOGIC_VECTOR(18DOWNTO0);BEGINPR0CESS(T2)BEGINIF(T2EVENTANDT2=1)THENDATA0UT(18DOWNTO

29、0)=O(18DOWNTO0);ENDIF;P2=DATAOUT(O);P1=DATAOUT(1);LDFR=DATAOUT(2)ANDT4;LED_B=DATAOUT(3);SW_B=DATAOUT(4);CS=DATAOUT(5);WR=DATAOUT(6)OR(NOTT3);LDDR=DATAOUT(7)ANDT4;LDAC=DATAOUT(8)ANDT4;ALU_B=DATAOUT(9);S0=DATAOUT(10);S1=DATAOUT(11);R2_B=(DATAOUT(13)OR(NOTI1)ORI0)AND(DATAOUT(12)OR(NOTI3)ORI2);R1_B=(DAT

30、AOUT(13)OR(NOTI0)ORI1)AND(DATAOUT(12)OR(NOTI2)ORI3);RO_B=(DATAOUT(13)ORI1ORI0)AND(DATAOUT(12)ORI3ORI2);LDR2=T4ANDDATAOUT(14)ANDI1AND(NOTI0);LDR1=T4ANDDATAOUT(14)AND(NOTI1)ANDI0;LDR0=T4ANDDATAOUT(14)AND(NOTI1)AND(NOTI0);LDIR=DATAOUT(15)ANDT3;LDAR=DATAOUT(16)ANDT3;LDPC=DATAOUT(17)ANDT4;LOAD=DATAOUT(18

31、);ENDPROCESS;ENDA;微地址轉(zhuǎn)換器F2LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYF2ISPORT(D:INSTD_LOGIC_VECTOR(5DOWNTO0);UA5,UA4,UA3,UA2,UA1,UAO:OUTSTD_LOGIC);ENDF2;ARCHITECTUREAOFF2ISBEGINUA5=D(5);UA4=D(4);UA3=D(3);UA2=D(2);UA1=D(1);UAO=D(O);ENDA;微地址轉(zhuǎn)換器F3LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYF3ISPORT(

32、D:INSTD_LOGIC_VECTOR(7DOWNTO0);UA7,UA6,UA5,UA4,UA3,UA2,UA1,UAO:OUTSTD_LOGIC);ENDF3;ARCHITECTUREAOFF3ISBEGINUA7=D(7);UA6=D(6);UA5=D(5);UA4=D(4);UA3=D(3);UA2=D(2);UA1=D(1);UA0=D(0);ENDA;3.12頂層電路單元備注：SF,和LDRF輸出是個(gè)人用于仿真差錯(cuò)時(shí)候加入的，對(duì)于機(jī)器不影響。3.13功能仿真與時(shí)序仿真iJmnB-OR7C(?0woopQ|W痕匕加*az*vwEWGJR酵FCHOCHR1笛M2且-C*s*|*111

33、1TittMtf啤區(qū)|12.6ms130ufcU&ib恰電泌1E*kbIlk-諂2jjwuifinnjuicinuutJinjiRjtJonjUuwjVmjuuojuuinnjWLnnmmnmnjunnnjia腫臺(tái)若血HMnnHOCH14HH吊Hf1HiHFBHFi両何l蟲(chóng)m-何何i葉廠帀-、聞何芮丙.血x韓:rnfaMfT*1Jhie-ie*w汕22hnMm1F.uiiiiihiiii.imuuviuiiiiiiriiuwiiiijuniiii.11111hiiiiuiiiiiiiiijiiiiihiiiiiiiiiiijiiiiimumi.muuiiihiiii.iiiiijiiiiiii

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