1、第9章 分頻電路的設(shè)計硬件描述語言和數(shù)字系統(tǒng)設(shè)計2主要內(nèi)容：9.1 2n分頻電路的設(shè)計9.2 2N分頻電路的Verilog描述9.3 5分頻電路設(shè)計常見錯誤分析9.4 奇數(shù)次分頻電路的Verilog描述39.1 2n分頻電路的設(shè)計知識點：9.1.1 D觸發(fā)器搭建的16分頻電路原理圖49.1.1 D觸發(fā)器搭建的16分頻電路原理圖5電路要點:1.本級的輸出端Q_接入D輸入端;2.本級的輸出Q或者Q_接入下級的CLK輸入端;3.經(jīng)過一個D觸發(fā)器進行21分頻；4.與16進制異步計數(shù)器電路圖是否相同？69.2 2N分頻電路的Verilog描述(以10分頻為例)知識點：9.2.1 10分頻的Verilog

2、描述9.2.2 10分頻的仿真波形9.2.3 10分頻綜合的RTL電路圖79.2.1 10分頻的Verilog描述/假設(shè)占空比為50%module clk10f (preclk, rst,clk10f);input preclk, rst;output clk10f;reg clk10f;reg 3:0 count;always (posedge preclk or posedge rst) if (rst) count = 4b0000; else if( count = 4b0100) count = 4b0000; else count = count + 4b0001;8always

3、(posedge preclk or posedge rst) if (rst) clk10f= 1b0; else if( count = 4b0100) clk10f = clk10f;endmodule 99.2.2 10分頻的仿真波形109.2.3 10分頻綜合的RTL電路圖119.3 5分頻電路設(shè)計常見錯誤分析知識點：error1-5分頻電路的電平描述error2-5分頻電路的兩個邊沿觸發(fā)error3-5分頻電路的多驅(qū)動問題129.3.1 error1-5分頻電路的電平描述/假設(shè)占空比為50%module divide5error(rst,clk,clk5);input rst,cl

4、k;output clk5;reg clk5;reg 2:0 counter; always (clk or rst) if (!rst) counter =3b000;else if(counter=3b100) counter =3b000;else counter = counter+1; always (rst or counter) if (!rst) clk5=1b0; else if(counter=3b100) clk5=clk5;endmodule13仿真波形分析: 從仿真波形上看,滿足5分頻要求,但是,綜合的電路情況是否同樣滿足呢?14Leonardo工具綜合的電路圖綜合時

5、報告的Warning:1. Warning, input clk is never used.2.Warning, clk5 is not always assigned. Storage may be needed.3.Warning, Design contains combinatorial loop through net counter(0), counter(1), counter(2).15分析-電平觸發(fā)簡化情況module seqorcombin(rst,clk,d,q);input rst,clk;input d;output q;reg q;always (clk or r

6、st)if (!rst)q=1b0;else q=d;Endmodule這是時序邏輯還是組合邏輯?或者你覺得它應(yīng)該是什么?16電平觸發(fā)的過程塊綜合結(jié)果綜合過程中的warning:1. E:/seqorcombin.v,line 2: Warning, input clk is never used.2. E:/seqorcombin.v,line 12: Warning, d should be present in the always condition.17module divide5error(rst,clk,clk5);input rst,clk;output clk5;reg cl

7、k5;reg 2:0 counter;always (posedge clk or negedge clk or negedge rst)if (!rst) counter =3b000;else if(counter=3b100)counter =3b000;else counter = counter+1; always (rst or counter) if (!rst) clk5=1b0;else if(counter=3b100) clk5=clk5;endmodule9.3.2 error2-5分頻電路的兩個邊沿觸發(fā)18仿真波形分析: 從仿真波形上看,滿足5分頻要求,但是,綜合的電

8、路情況是否同樣滿足呢?19 Leonardo工具綜合的電路圖綜合時報告的ERROR:E:/divide5_error/divide5error.v, line 28: Error, Always block sensitive to both positive and negative edge of clk and clk can not be synthesized為什么?(以D觸發(fā)器說明,上跳沿和下跳沿同時觸發(fā)可以嗎?)always (posedge clk or negedge clk or negedge rst)if (!rst)q=1b0;else q=d;20 9.3.3 Er

9、ror3- 5分頻電路的多驅(qū)動問題module divide5 (rst,clk,clk5);input rst,clk;output clk5;reg clk5;reg 2:0 counter; always (rst or counter) if (!rst) clk5=1b0;else if(counter=3b100) clk5=clk5;21always (posedge clk or negedge rst)if (!rst) counter =3b000;else if(counter=3b100)counter =3b000;else counter = counter+1;a

10、lways (negedge clk or negedge rst)if (!rst) counter =3b000;else if(counter=3b100)counter =3b000;else counter = counter+1;endmodule22仿真波形(滿足5分頻占空比為50%的要求)但是綜合結(jié)果呢?239.4 奇數(shù)次分頻電路的Verilog描述(以5分頻為例)知識點：5分頻的Verilog描述-正確方法一5分頻的Verilog描述-正確方法一 testbench5分頻的Verilog描述-正確方法二5進制計數(shù)器的Verilog錯誤表達15進制計數(shù)器的Verilog錯誤表達

11、25進制計數(shù)器的Verilog錯誤表達3249.4.1 5分頻的Verilog描述-正確方法一/假設(shè)占空比為50%module d5f(clk,rst,clk5f); input clk,rst; output clk5f; wire clk0; wire clk5f; reg 2:0 counter1,counter2; reg clk5f1,clk5f2; assign clk0=clk;25 always (posedge clk or negedge rst) if(!rst) counter1=0; else if(counter1=3b100) counter1=0; else c

12、ounter1=counter1+1; always (posedge clk or negedge rst) if(!rst) clk5f1=0; elseif(counter1=3b100)|(counter1=3b010) clk5f1=clk5f1; 26 always (posedge clk0 or negedge rst) if(!rst) counter2=0; else if(counter2=3b100) counter2=0; else counter2=counter2+1; always (posedge clk0 or negedge rst) if(!rst) c

13、lk5f2=0; else if(counter2=3b100)|(counter2=3b010) clk5f2=clk5f2; assign clk5f=clk5f1|clk5f2; endmodule 275分頻的仿真波形285分頻綜合后的電路圖29 module tb_G5f; reg clk,rst; wire clk5f; always #50 clk=clk; initial begin clk=0; rst=1; #5 rst=0; #5 rst=1; end /module d5f(clk,rst,clk5f); d5f hw(.clk(clk),.rst(rst),.clk5

14、f(clk5f);endmodule 9.4.2 5分頻的Verilog描述-正確方法一testbench30 9.4.3 5分頻的Verilog描述-正確方法二 /假設(shè)占空比為50%思想方法： 能否利用偶數(shù)分頻2N設(shè)計思想（轉(zhuǎn)化為對時鐘信號的N計數(shù)器設(shè)計，在計時器計滿一次N時， 2N分頻信號反向一次）； 如果能對奇數(shù)分頻M進行時鐘信號半周期的M計數(shù)，那么當計時器計滿一次M時，分頻信號M反向一次）31 5進制計數(shù)器的Verilog描述 要求：對時鐘信號clk半周期記一次數(shù)32/假設(shè)占空比為50%module d5f(clk,rst,clk5f); input clk,rst; output c

15、lk5f; reg clk5f; reg 3:0 counter1,counter2; reg 4:0 counter_temp, counter;33 always (posedge clk or negedge rst) if(!rst) counter1=0; else if(counter1=4b1001) counter1=0; else counter1=counter1+1;34 always (negedge clk or negedge rst) if(!rst) counter2=0; else if(counter2=4b1001) counter2=0; else co

16、unter2=10) counter=counter_temp-10; else counter=counter_temp;36 always (rst or counter) if(!rst) clk5f=0; else if(counter=4b0) clk5f=0; else if(counter=4b0101) clk5f=1;endmodule 37 5進制計數(shù)器方法二-仿真波形38 5進制計數(shù)器方法二-綜合結(jié)果綜合結(jié)果：Clk5f 會有鎖存器產(chǎn)生分析： 此處Clk5f需要鎖存器。39 9.4.4 5進制計數(shù)器的Verilog錯誤表達1module counter_error1(cl

17、k, rst, counter); input clk, rst; output 2:0 counter; reg 2:0 counter; always (clk or rst) if (rst) counter =3b000; else if (counter=3b100) counter = 3b000; else counter = counter+ 3b001;endmodule問題：這是時序邏輯還是組合邏輯?40 5進制計數(shù)器的Verilog錯誤表達1-仿真波形分析：仿真波形滿足要求，但是綜合結(jié)果呢？41 5進制計數(shù)器的Verilog錯誤表達1-綜合結(jié)果綜合時報告的Warning:

18、 1.Warning, input clk is never used.2.Warning, Design contains combinatorial loop through net counter(0),counter(1), counter(2), counter(3).42 5進制計數(shù)器的Verilog錯誤表達1-綜合結(jié)果 錯誤原因：過程塊使用電平觸發(fā)方式，在綜合時被映射成組合邏輯電路； 描述計數(shù)器這樣的時序邏輯，其敏感量不能采用電平觸發(fā)方式！439.4.5 5進制計數(shù)器的Verilog錯誤表達2module counter_error2(clk, rst, counter); in

19、put clk, rst; output 2:0 counter; reg 2:0 counter; always (posedge clk or negedge clk or posedge rst) if (rst) counter =3b000; else if(counter=3b100) counter = 3b000;else counter = counter+ 3b001;endmodule問題：這種描述方式問題出在什么地方？44 5進制計數(shù)器的Verilog錯誤表達2-仿真波形分析：仿真波形滿足要求，但是綜合結(jié)果呢？45綜合工具不能映射成電路，報告的錯誤信息: Error:

20、Always block sensitive to both positive and negative edge of clk and clk can not be synthesized！錯誤原因分析：同一個D觸發(fā)器能夠既用時鐘信號的上升沿又用下降沿來觸發(fā)嗎？ 所以，應(yīng)改正為： always (posedge clk or posedge rst)或者 always (negedge clk or posedge rst)469.4.6 5進制計數(shù)器的Verilog錯誤表達3module counter_error3(clk, rst, counter); input clk, rst; output 2:0 counter; reg 2:0 counter; always (posedge clk or posedge rst) if (rst) counter =3b000; else if(count