1、Xilinx IP核設(shè)計(jì)FIR濾波器ISE 版本 12.4啟動(dòng)ISEFile-New ProjectNextNext-Finish在ISE的設(shè)計(jì)啟動(dòng)視圖中View： ()ImplefTiGntati on CjSimul ationXi erarchy遁 Firfilter白-O xc6 slx43t qgl44LJJ Unassigned. User Library ModulesEmpty ViewThe view currently con tai ns no Files. You can add files to the project using the toolbar at lef

2、tcommands from the Project menuand by using the Design, File勺 and Libr-aries panels.Use: New Source: To create a new source file.Add Source; To add an existing File to the project.Add Copy of Source; To copy an existing file to the project directory and add it to the project.在空白處右鍵，選擇New Source,彈出對(duì)話

3、框New Source izardS皀lect Sour ce： TypeSelect source type? file name and its locatiorv| 售 IP (CORE Generator | 售 IP (CORE Generator & Architecture Wizard.)選擇新建類(lèi)型為IP coreUser DocwrientVerilog ModuleVerilog Test FixtureVJffiL ModuleVJffiL LibraryUser DocwrientVerilog ModuleVerilog Test FixtureVJffiL Mod

4、uleVJffiL LibraryVMDL PackageVMDL Test BenchEmbedded ProcessorFile iLame：irl6設(shè)置IP core名Locati on：x12.4ISE JSprojectFirfilt-&rXipcBe_dir .0Add to project衛(wèi)倘0Add to project衛(wèi)倘t ” I CancelNext,彈出對(duì)話框Next-Finisht FIR Compiler詳細(xì)說(shuō)明可以點(diǎn)擊Documents中的uolu menis i yiuuvFreq. ResponseDatasheetFrmquQncy Response (Ma

5、gnitude)so1010*02040Normalized Frequenizy (x PI rad/sample)(ap) prqcww20Set to Display : so1010*02040Normalized Frequenizy (x PI rad/sample)(ap) prqcww20Set to Display : 1Range: 1.1Range : |o.O| - 0.5| 0.5 1,0 十自己設(shè)置。可以根據(jù)需要設(shè) 置任意的帶通，帶阻Min :18.061800 dBMax :43.525674 dB21.583625 dBRipple : 25.463874 dB

6、Filter AnalysisPassbandStop bandComponent NamefineFilter CoefficientsSelect Source :VectorvCoeffi匚ient Vector : 6,043,5.6,-6,-13,7,44,64,44,7Next-Finish在文件中編輯Verilogtimescale Ins / Ips/ Compa ny:/ Engineer:/ Create Date:14:40:35 04/18/2011/ Design Name:/ Module Name:fir/ Project Name:/ Target Device

7、s:/ Tool versions:/ Description:/ Dependencies:/ Revision:/ Revision 0.01 - File Created/Additional Comments:/llllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllmodule fir(s axis data tready, s axis data tvalid, m axis data tvalid, aclk, m axis data tdata,s_axis_data_t

8、data);output s_axis_data_tready;in put s_axis_data_tvalid;output m_axis_data_tvalid;in put aclk;output 23 : 0 m_axis_data_tdata;in put 15 : 0 s_axis_data_tdata;firl6firl6(.s_axis_data_tready(s_axis_data_tready),.s_axis_data_tvalid(s_axis_data_tvalid)/.m_axis_da ta_tvalid(m_axis_data_tvalid)/.aclk(ac

9、lk)/.m_axis_data_tdata(m_axis_data_tdata),.s_axis_data_td ata (s_axis_d ata_tdata)； en dmodule在ISE設(shè)計(jì)啟動(dòng)視圖右鍵,New SourceNext-Next-Finish 編輯測(cè)試文件fir_tb timescale Ins / Ips/ Compa ny:/ Engineer:/ Create Date: 15:03:58 04/18/2011/ Design Name:fir/ Module Name: F:/Xilinx/12.4/ISE_DS/project/Firfilter/fir_tb

10、.v/ Project Name: Firfilter/ Target Device:/ Tool versions:/ Description:/ Verilog Test Fixture created by ISE for module: fir/ Dependencies:/ Revision:/ Revision 0.01 - File Created/Additional Comments:/llllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllmodule fir_tb;/

11、Inputsreg s_axi s_d a ta_t va lid;reg aclk;reg 15:0 s_axis_data_tdata;reg 15:0 Mem37:0);/ Outputswire s_axis_data_tready;wire m_axis_data_tvalid;wire 23:0 m_axis_data_tdata;integer kJ;/ Instantiate the Unit Under Test (UUT)fir uut (s_axis_data_tready(s_axis_data_tready),s_axis_data_tvalid(s_axis_dat

12、a_tvalid),m_axis_data_tvalid(m_axis_data_tvalid),aclkfaclk),m_axis_data_tdata(m_axis_data_tdata),s_axis_data_tdata(s_axis_data_tdata)initial begin/ Initialize Inputs/s_axis_data_tvalid = 1; s_axis_data_tvalid = 0;for(i=0;i40;i=i+l)begin#90 s_axis_data_tvalid = 1;#10 s_axis_data_tvalid = 0;endendin i

13、tial/clock gen eratebeginaclk = 0;forever #5 aclk=!aclk;endinitial $readmemh(,data_in.txt,/Mem);/ Add stimulus here/Data in put Gen erationinitial begins_axis_data_tdata = 0;for(k=0;k3 8;k=k+l)#100 s_axis_data_tdata = Memk; enden dmodule在工程文件夾卞新建datajn.txt,輸入0001 0002 0001 0008 0001 0001 0000 0008 0

14、001 0001 0002 0001 0001 0002 0001 0000 00010002 0004 0008 0000 0001 0002 0001 0008 0001 0001 0000 0008 0001 0001 0002 0001 0001b癮 Simulati onb癮 Simulati onVi ew： O Implementa|.LQii QBehavi oralHi erar chyFirHlter- O xc6slx43tqg：144 選中 fir_tb 后,進(jìn)程窗I 1 顯示如下,分別選擇 Behavioral Check Syntax 和 Simulate Beha

15、vioral Model,右鍵，點(diǎn)擊runSISIFreesses: ir_tb曰綜 ISiffi Sirriul a.tor身 Behavior al Check SyntaxSimul ate B ehavi or al N o del顯示濾波結(jié)果:(OKU- ooooooooc設(shè)置為5us就能看見(jiàn)全部38個(gè)數(shù)據(jù)的濾波結(jié)果OOOOOOCOXOOOOK (OOOOOCOXOOOOCi： OOOOOOCOXOOOOtta.BXtx. 電 gIS O)(OKU- ooooooooc設(shè)置為5us就能看見(jiàn)全部38個(gè)數(shù)據(jù)的濾波結(jié)果OOOOOOCOXOOOOK (OOOOOCOXOOOOCi： OOOO

16、OOCOXOOOOtta.BXtx. 電 gIS O)Rf3M ( o 丁3；onw-irooo-y)cof wiw ，師“ /( GOOS,j*幣ST nWiO- rHWT-* 空“”枷 H妙H辛 CO啲啲啲啲申 iWiWiWiwli1 WiWiWtwi0|(KOiWHWiWiwii.IWI ；0iwi-* VOII*-；ZOOIOO- iwwy JwWiWiWiwiCOl(k W1G io U*5C ccr M對(duì)濾波結(jié)果進(jìn)行驗(yàn)證：在IP Core設(shè)置中，生成濾波器根據(jù)設(shè)置的帶通帶阻生成了濾波器的抽頭系數(shù)。Coefficient Victor : 604廠356-6廠1324去64,44憶-13廠665廠3,766啟動(dòng)Matlab 在命令窗I I中輸入 b = 60-4-3 5 6 -6 L3 ?