數(shù)字系統(tǒng)設計與VHDL(第3版）數(shù)字系統(tǒng)設計與VHDL（第3版）第11章

TestBench測試與時序分析

11.1TestBench測試11.2TestBench測試實例11.3ModelSimSE使用指南11.4時序約束與時序分析激勵模塊（stimulus）類似于一個測試向量發(fā)生器（testvectorgenerator），向待測模塊（DesignUnderTest，DUT）施加激勵信號，輸出檢測器（outputchecker）檢測輸出響應，將待測模塊在激勵向量作用下產(chǎn)生的輸出按規(guī)定的格式和方式（波形、文本或者VCD文件）進行展示，供用戶檢查驗證。11.1.1TestBench11.1TestBench測試例11.1產(chǎn)生復位信號。ENTITYreset_genISENDENTITY;ARCHITECTUREarchOFreset_genISSIGNALreset:BIT;BEGINreset<='0','1'AFTER50

ns,'0'AFTER100

ns;ENDarch;11.1.2

用VHDL描述激勵信號例11.3周期脈沖信號的產(chǎn)生。LIBRARYIEEE;USEIEEE.std_logic_1164.all;ENTITYwave_genISENDwave_gen;ARCHITECTUREarchOFwave_genISSIGNALwave:STD_LOGIC;BEGINPROCESSBEGINwave<='0'; WAITFOR40

ns;wave<='1'; WAITFOR40

ns;wave<='0'; WAITFOR40

ns;wave<='1'; WAITFOR40

ns;wave<='1'; WAITFOR40

ns;wave<='1'; WAITFOR40

ns;ENDPROCESS;ENDarch;11.1.2

用VHDL描述激勵信號例11.6產(chǎn)生占空比為1/3的時鐘信號。LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYclk_gen3ISENDclk_gen3;ARCHITECTUREoneOFclk_gen3ISSIGNALclk:STD_LOGIC;CONSTANTperiod:TIME:=30

ns;BEGINCLK_GEN:PROCESSBEGINclk<='1';WAITFORperiod/3;clk<='0';WAITFOR2*period/3;ENDPROCESS;ENDone;例11.11奇校驗產(chǎn)生電路的VHDL描述。LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYodd_parityISPORT(a:INSTD_LOGIC_VECTOR(2DOWNTO0);odd:OUTSTD_LOGIC);ENDENTITY;ARCHITECTURErtlOFodd_parityISBEGINPROCESS(a)VARIABLEsum,r:INTEGER;BEGINsum:=0;FORiIN2DOWNTO0LOOPIFa(i)='1'THENsum:=sum+1;ENDIF;ENDLOOP;r:=summod2;IF(r=0)THENodd<='1';ELSEodd<='0';ENDIF;ENDPROCESS;ENDrtl;11.2TestBench測試實例例11.12奇校驗產(chǎn)生電路的TestBench測試代碼。LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYodd_parity_tbISENDodd_parity_tb;ARCHITECTUREarchOFodd_parity_tbISCOMPONENTodd_parityPORT(a:INSTD_LOGIC_VECTOR(2DOWNTO0);odd:OUTSTD_LOGIC);ENDCOMPONENT;SIGNALtest_in:STD_LOGIC_VECTOR(2DOWNTO0);SIGNALtest_out:STD_LOGIC;BEGINi1:odd_parityPORTMAP(a=>test_in,odd=>test_out);--DUT例化PROCESSBEGINtest_in<="000";WAITFOR200

ns; test_in<="001";WAITFOR200

ns; test_in<="010";WAITFOR200

ns; test_in<="011";WAITFOR200

ns; test_in<="100";WAITFOR200

ns; test_in<="101";WAITFOR200

ns; test_in<="110";WAITFOR200

ns; test_in<="111";WAITFOR200

ns;ENDPROCESS;例11.14二進制碼轉(zhuǎn)格雷碼的測試程序。PROCESSVARIABLEerror_status:BOOLEAN;BEGINWAITONtest_in;WAITFOR100

ns;IF((test_in="000"andtest_out='1')or(test_in="001"andtest_out='0')or(test_in="010"andtest_out='0')or(test_in="011"andtest_out='1')or(test_in="100"andtest_out='0')or(test_in="101"andtest_out='1')or(test_in="110"andtest_out='1')or(test_in="111"andtest_out='0'))THENerror_status:=FALSE;ELSEerror_status:=TRUE;ENDIF;ASSERTNOTerror_status --錯誤報告REPORT"TESTFAILED!"SEVERITYerror; ENDPROCESS;ENDarch;奇校驗產(chǎn)生電路的ModelSimSE仿真波形圖11.3ModelSimSE使用指南例11.8帶異步復位、同步置數(shù)的模24BCD碼加法計數(shù)器代碼。LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYcnt24bcdISPORT(clk:INSTD_LOGIC; --時鐘en:INSTD_LOGIC; --使能端clr:INSTD_LOGIC; --清零端，高電平有效ld:INSTD_LOGIC; --置數(shù)端，高電平有效d:INSTD_LOGIC_VECTOR(7DOWNTO0); --置數(shù)數(shù)據(jù)cout:OUTSTD_LOGIC; --進位輸出qh:OUTSTD_LOGIC_VECTOR(3DOWNTO0); --十位ql:OUTSTD_LOGIC_VECTOR(3DOWNTO0)); --個位ENDcnt24bcd;ARCHITECTUREoneOFcnt24bcdISSIGNALtemp:STD_LOGIC_VECTOR(7DOWNTO0);BEGINcout<='1'WHEN(temp=X"23"ANDen='1')ELSE'0';PROCESS(clk,clr)BEGINIF(clr='1')THENtemp<="00000000";ELSEIF(clk'EVENTANDclk='1')THENIF(ld='1')THENtemp<=d;ELSIF(en='1')THENIF(temp(3DOWNTO0)=3andtemp(7DOWNTO4)=2)ortemp(3DOWNTO0)=9THENtemp(3DOWNTO0)<="0000";IFtemp(7DOWNTO4)=2THENtemp(7DOWNTO4)<="0000";ELSEtemp(7DOWNTO4)<=temp(7DOWNTO4)+'1';ENDIF;ELSEtemp(3DOWNTO0)<=temp(3DOWNTO0)+'1';ENDIF;ENDIF;ENDIF;ENDIF;ENDPROCESS;qh<=temp(7DOWNTO4);ql<=temp(3DOWNTO0);ENDone;11.3ModelSimSE仿真實例例11.9模24BCD碼加法計數(shù)器的TestBench測試代碼。LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYcnt24_tsISENDcnt24_ts;ARCHITECTUREoneOFcnt24_tsISCONSTANTcycle:TIME:=40ns;SIGNALclk,clr:STD_LOGIC;SIGNALcout:STD_LOGIC;SIGNALd:STD_LOGIC_VECTOR(7DOWNTO0);SIGNALen,ld:STD_LOGIC;SIGNALqh:STD_LOGIC_VECTOR(3DOWNTO0);SIGNALql:STD_LOGIC_VECTOR(3DOWNTO0);COMPONENTcnt24bcdPORT(clk:INSTD_LOGIC;clr:INSTD_LOGIC;cout:OUTSTD_LOGIC;d:INSTD_LOGIC_VECTOR(7DOWNTO0);en:INSTD_LOGIC;

ld:INSTD_LOGIC;qh:OUTSTD_LOGIC_VECTOR(3DOWNTO0);ql:OUTSTD_LOGIC_VECTOR(3DOWNTO0));ENDCOMPONENT;BEGINi1:cnt24bcd --待測模塊例化PORTMAP(clk=>clk,clr=>clr,cout=>cout,d=>d,en=>en,ld=>ld,qh=>qh,ql=>ql);init:PROCESSBEGINclr<='1';ld<='0';en<='0';WAITFORcycle*2;clr<='0';WAITFORcycle*2;en<='1';WAITFORcycle*32;d<="00011000";WAITFORcycle*2;ld<='1';WAITFORcycle*4;ld<='0';WAIT;ENDPROCESSinit;always:PROCESSBEGINclk<='1';WAITFORcycle/2; --產(chǎn)生clk時鐘clk<='0';WAITFORcycle/2;ENDPROCESSalways;ENDone;ModelSimSE的啟動界面和工作界面新建工程項目填加仿真文件新建仿真文件輸入仿真文件代碼并編譯編譯文件到work工作庫并加載將Objects窗口中信號加載至Wave窗口查看功能仿真波形圖和文本輸出（ModelSimSE）11.4時序約束與時序分