iEDA

MakingOpenSiliconDesignEverywhere

UsingCloud-basedOpenAgileEDAPlatform

XueyanZhao

<zhaoxueyan21b@>

ECOSTeamofCenterforAdvancedComputerSystems,

InstituteofComputingTechnology,ChineseAcademyofSciences

OpenSource@Siemens2025一Wuxi,China

Oct30-31,2025

Aboutus(BuildOpenSiliconEcosystem!)

1.startfrom2020(>6Kstars,>730forkonGithub)

2.highestperformingopen-sourceprocessorseries

Xiangshan(processor)

iEDA

iEDA/AiEDA(physicaldesigntools)

1.startfrom2020(open-sourceEDA)

2.havesiliconproveninproperty110nm/28nm

?ArealBIGteam(ledbyProf.YungangBao)

ECOSTEAM

SNOW

(IPcomponents)

(designflow)

ECOSStudio

(cloudplatform)

1.startfrom2019(involve12000+studentsinChina)

2.provideFREEfrontendandbackendcoursesonline

weAREHERE(*^▽^*)

“OneStudentOneChip”Initiative(education)

1.startfrom2024(focusonopenASICdesignservice)

2.integrateIPcomponents,flowandcloudplatform

SNOW(Shuttle-NO-Wait,designservice)

2025/11/21OpenSource@Siemens20254/27

2025/11/21OpenSource@Siemens20255/27

ECOSTeam:ProvideASICFull-stackSolutions

?tape-out10+chips/year(IPDesign/SoCIntegrate/PhysicalDesign/Package/Bring-up)?cover130/110/55/40/28nm,10K~10Minstances,100MHz~1.5GHz,multiplepower/clockdomains?designopen-sourceprocessors(canbootLinux)andIPs(UART,TIMER,QSPI,I2S,I2C,VGA,PSRAM…)

?developiEDA(iEDAjustfocusonPDstagenow)

?servestudentsandseveralinstitutions(OneStudentOneChip,NU.Kazakhstan,…)

Sometape-outedchipsofourteam:

?developECOSStudio(cloudplatform)withYosys+iEDAbasedonICS55OpenPDK(ongoing)

TheOpenSiliconTechnicalRoadmapofECOSTeam

2021-2024:PropertyEDA(synthesis,floorplan)andiEDA(PDstage)mixeduse

2022-2025:Developandtryopen-sourceflowbasedoniEDAandSKY/IHP130/ICS55PDK

2025-2030:OpenFULLRTL2GDSflows(Yosys+iEDA+ICS55OpenPDKonECOSStudio)

“OneStudentOneChip”Initiative

ExternalCollaborationProject

Tape-outbyusingiEDAin110/55/28nm

2025/11/21OpenSource@Siemens20256/27

Highlight

?TeachphysicaldesignwithcloudplatformECOSStudio(Yosys+iEDA+ICS55)

?Introduceaneducation-orientedchipretroSoCtape-outedinSMIC/SKY130

?SharesomeofthelatestinformationoniEDAtoolchains

+

+

iEDA

2025/11/21OpenSource@Siemens20257/27

WHYwedevelopECOSStudio?

?Getmorestudentsexcitedaboutopensilicondesign(justforfun!)

?encourageenthusiastssharetheirideasorthinkingswiththecommunity

?helpmorestudentsinvolvedinEDAalgorithm(designasimplesynthesistool~)

?Fillthegapbetweenindustryandacademic(community-oriented)

?propertytoolsareincrediblyexpensiveanduncontrolled(geopoliticaluncertainties)

?increasingactualdemandsfromindustrybacktoacademic

?newEDAalgorithmsfromacademicneedaseriesoftrialsbeforeapplyingtoindustry

?Eraseperformancedifferencesfromlocalcomputer(usingcloudclusters!)

?physicaldesigntoolseattoomuchmemoryandCPUresources(ToT)

?meetdifferentlearners’needsfromdifferentcountriesandregions

?ProvideanOPENsolutionforthepotentialcommercialmarketplace

2025/11/21OpenSource@Siemens20258/27

AdvancedeXtensibleLayoutEditor

SoCTemplate

SelectSoCtemplatefromtheIPMarket

FloatPanelSystem

Supportthedragging,resizingoperationsandcustomizeddata

Real-timeCollaboration*

Architecture

RTL/VerifyBackend

PipelineMode

*:thisfeaturewillbereleasedin2025Q4

Flow

Cloud-basedAgileEDAPlatform

ECOSStudio

“ComponentizationofData”

iEDAInside

“Anopen-sourceEDAinfrastructure”

(supportICS55/SKY130/IHP130)

Dashboard

SynthesisFlow

MergetoLatestShuttle

2025/11/21OpenSource@Siemens20259/27

PartialKeyProcesses

CreateProject

4------------

1.fillprojectname

2.addsocialinfo

3.selectlicense

RunCTS

1.startprocess

2.showanimation

3.highlightbuffers

RunPlacement

1.startprocess

2.displayreports

3.showcongestion

ShowDRC

------------?

1.startprocess

2.displayDEFfile

3.showDRCmarks

DemonstratephysicaldesignprocessprovidedbyanundergradfromOneStudentOneChipInitiative(design:single-cycleprocessor,~3000cellsinIHP130)

2025/11/21OpenSource@Siemens202510/27

RenderEngineofECOSStudio:AXLE

?AXLE:AdvancedeXtensibleLayoutEditor

?keycomponentofECOSStudio

?supportDEF,highlight/multilayeroperations

?Performanceevaluation

?offlinerendering(webGPUbackend)

?3Mgraphicitems(~60Kgates),render4layers(4/11)

?consume3GBmemory,800MGPU,~30FPSrate

?opt.methods:culling,texturecache,offloadtoGPU

?Technicalroadmap(2025Q3~Q4)

?supportLEF/DEFandGDSformat

?supportfloorplan/powerplanonline.

?improveperf.(support1Mgates,<2GB,>=25FPS)

?webGL/webGPU+gRPC+Rustserver?integrate/supportNgspicesimulator

3MGraphicItemsRendering(perf.evaluation)

2025/11/21OpenSource@Siemens202511/27

ECOSStudio:VSCodePlugin/Client

?developVSCodeplugin(2026Q2~Q3)

?offerbettereditingexperienceforusers

?edit/submitcodes(RTL,Cprograms…)toECOSStudio

?DesktopclientofECOSStudio(2026Q2~Q4)

?supportprivatedeploymentinlocalnetwork

?removelimitationsofrenderingpoweredbybrowser

?openmoresystempermissiontousers

?customizeUIStyle(backgroundimages/font/skin…)

?providelocalhostAPIservices(Serial,USBandAudio)

?optimizefortouch-supporteddevices(tablet)

?implementspecification

?targetplatform:Win/MacOS/Linux(x64)

?basedonPython+Tarui2.0(Rust)

2025/11/21OpenSource@Siemens202512/27

ECOSStudioEngine:iEDARTLtoGDS

?Anopen-sourceEDAinfrastructureandtools(startfrom2020)

?11subtools,400K+linescode,testtape-out6times

?project

:https://ieda.oscc.cc/e

n

?code

:/OSC

C

-Project/iED

A

?DevelopChipCompiler(Flow,supportICS55,IHP/SKY130)

practice

design

2025/11/21OpenSource@Siemens202513/27

iEDA/iPD:PhysicalDesignToolchain

RTL

LogicSynthesis

Netlist

LogicCompiler

LogicOptimization

TechnologyMap

Formal

/OSCC-Project/iEDA

iNO

iFP

iPDN

iPL

iCTS

iTO

iRT

NetlistOptimization

Floorplanning

PowerDeliveryNetwork

PhysicalDesign

?11toolscompleted,5inactivedevelopment,300Klinescode

?well-organizedopen-sourceinfrastructuresupportsEDAdevelopmentandresearch

Placement

Analysis

RCExtraction

StaticTimingAnalysis

PowerAnalysis

IRDrop

Electromigration

FunctionalModule

iEDA-Interface

iEDA-

Operator

Solver

Analyzer

Evaluator

Reporter

Utility

iEDA-

Manager

Tool

Data

ClockTreeSynthesis

TimingOptimization

Routing

EngineeringChangeOrder

Filler

Sign-off

GDSII

Initial_placer

global_placer

iSTA

iPA

iPL

Config

API

post_global_placer

legalizer

FunctionalModule

Database

(Wrapper)

DB-APIiEDA-Database

detail_placer

buffer_inserter

iPL

filler_inserter

PhysicalVerificationDesignRuleCheck

checker

iDRC

evaluator

grid_manager

ElectronicRuleCheck

Output(.v/.def)

Input

(.v/.lef/.def/.lib/.sdc)

topo_manager

Layoutvs.Schematic

2025/11/21OpenSource@Siemens202514/27

iEDALatestUpdates:EnhancedDRCEngine

?SupportALLDRCRulesin28nmnode.

?Thesingle-passDRCtimeislessthan3sin100Kinstancesdesign(routingstage).

?ComparedtoCommercialtools,theaccuracyofthemajordesignrulesisabove95%.

?WiththenewversionofDRCengine,theQoRofiRThavebeensignificantlyimproved.

DRCVisulization

SupportAlmostDRCRulesinN28:

?CutDifferentLayerSpacing

?CutEOLSpacing

?CutEnclosure

?CutEnclosureEdge

?CutSpacing

?MetalCornerFillingSpacing

?MetalEOLSpacing

?MetalJogToJogSpacing

?MetalNotchSpacing

?MetalParallelRunLengthSpacing

?MetalShort

?MinHole

?MinStep

?MinimalArea

ComparedtoCommercialToolsinN28

2025/11/21OpenSource@Siemens202515/27

iEDALatestUpdates:EnhancedTimingOpt.Flow

?Exploringdifferentiabletiming-drivenplacement,path-basedbufferingandsensitivity-guidedgatesizing,etc.

?Weused50datasets,ranginginsizefrom10Kto4M.

?Comparingoursuggestfreq.resultswithcommercialtools,35+casesshowclosedperformancetocommercialtools.

2025/11/21OpenSource@Siemens202516/27

ANEWOpenPDKinChina:ICsprout55nm

?ICSproutSemicond.isaChinesefoundry(foundedin2021)

?jointlyestablishedbyZhejiangProvincialGovernmentandZJU

?haveadvanced12-inchCMOS180/55nmprocesslines

?55nm-CMOS,55nm-eFlash,180nm-BCD

?collaboratewithuniversities,academiaandindustryinChina

openits55nm-CMOSPDKin2025

?

?URL:

(/openeco

s-projects/icsprout55-pd

k)

?MPWtape-outcost(55nmCMOSOpenPDK)

?Independent:30~40Kyuan/mm^2($4,182~$5,576/mm^2)

?FullMask(600mm^2):10Kyuan/mm^2($1,395/mm^2)

?BringICSprout55nmOpenPDKintoECOSStudio

?establishstrongcooperationwithICSprout(What’vewedone):?portourdesignsandbackendflowsintoICSprout55nmOpenPDK?tape-outFIRSTtestchiponICSprout55nmOpenPDKinJune15,2025

Design:ARV32IMACSoC(PSRAM,QSPI,UART,I2C,PWM,TIMER,RNG).

Size:4mm^2(128KBOCM,noPLL)

Freq:100MHz(externalclockbypass)

Gates:1.517M(73,009cells)

?helptotryPDflowandgivefeedbackstoICSproutforbugsfixingPower:115.4mW(dynamic)0.42mW(static)

developOPEN-SOURCEPLLandDDR3PHYbasedonICSprout55nmOpenPDK(ongoing)

2025/11/21OpenSource@Siemens202517/27

DesigningChipswithiEDAonICsprout55nm

?WeattemptedtodesignaSoC(70Kinstances,fromOSOC)onICSprout55nmtechnologyinJune

?DRCcleancanbeachievedonallmetallayersexceptM1andtimingcanapproachconvergence

ThenumberofDRC

2025/11/21OpenSource@Siemens202518/27

DesigningChipswithiEDAonICsprout55nm

?M1PinShapesaresomewhatdifferentfromotheroptimizedprocesses：

?TheM1enclosureisdifficulttobeenclosedbytheM1PinShapemetal

?PinaccessbecomesasignificantsourceofDRCissues

?Solution：Usethepre-processedM2shapeinLEFfiletocompletepinaccess

?UsingthissolutionswecanachieveDRCclean

PinShape&Metal

M2AccessPinShape

2025/11/21OpenSource@Siemens202519/27

DesigningChipswithECOSstudioinDecember

?Wewillstartanewtape-outprojectinDecember

?WewillallowOSOCstudentsandOpen-Sourceenthusiaststoparticipateinthistape-out

?Thenumberofinstancesneedstobelessthan100K

?Thefrequencyofthedigitalchipshouldbelessthan100M

?SRAMandPLLIPareworkinginprogress

ScanQRcodeformoredetails

?Initiallywereceived20chips(8K-20Kinstances)fromOSOCstudents

DesignName

#gates

#nets

#inst

#macros

#IO

density

Freq.

WNS

TNS

RT

#DRC

stage_b_ysyx_23060170

46161

10902

13790

0

387

0.309125

100M

5.233

0

326.28

0

stage_b_ysyx_23060203

53054

11573

14748

0

387

0.322115

100M

4.899

0

320.12

0

stage_b_ysyx_23060229

49370

11837

15003

0

387

0.300443

100M

4.908

0

366.31

0

stage_b_ysyx_23060246

47717

11671

15436

0

387

0.223396

100M

5.193

0

330.83

0

stage_b_ysyx_24070003

58082

11820

16765

0

387

0.173035

100M

3.168

0

335.21

0

stage_b_ysyx_24080032

49464

10661

13745

0

387

0.316553

100M

3.903

0

325.14

0

stage_b_ysyx_24100012

47286

10988

14046

0

387

0.306919

100M

5.828

0

318.89

0

stage_b_ysyx_24110017

52414

12014

15779

0

387

0.246557

100M

5.545

0

343.54

0

stage_b_ysyx_25010008

52717

11489

14654

0

387

0.321606

100M

5.281

0

309.45

0

stage_b_ysyx_25010030

41986

11751

15251

0

387

0.208437

100M

3.507

0

326.11

0

stage_b_ysyx_25020037

51491

10975

14115

0

387

0.318805

100M

3.835

0

347.71

0

stage_b_ysyx_25040129

48055

10605

14133

0

387

0.236888

100M

6.273

0

288.64

0

stage_d_ysyx_24080018

47106

12640

15913

0

177

0.282335

100M

5.122

0

397.51

0

stage_d_ysyx_24090003

51573

12205

15520

0

177

0.309766

100M

3.04

0

411.68

0

stage_d_ysyx_25010009

58400

12606

16776

0

177

0.240029

100M

2.664

0

424.49

0

stage_d_ysyx_25020042

36498

10185

13498

0

177

0.215315

100M

3.911

0

328.73

0

stage_d_ysyx_25070198

49084

7643

10477

0

177

0.371986

100M

5.007

0

273.18

0

stage_d_ysyx_25080207

46038

7525

10198

0

177

0.381063

100M

5.56

0

287.3

0

2025/11/21OpenSource@Siemens202520/27

HowtobringuserstoECOSStudio/ICS55PDK

?ForstudentsfromOneStudentOneChip

?tape-outasingle-cycleprocessorinStageD

?completeHW/SW,passonlineassessment(OSOCtutorial)

?completePDflow,mergedesigntoSoCtemplate(ECOSStudio)

?designisverysmall

?impl.8instructions+axi4l,canrun“SuperMario”

Later,we’llgiveabriefintroduction

?~3848cells,0.011mm^2inICS55,DRCnum<10,~100yuan($14)

?tape-outFORFREE(forChinesestudents)

?designtutorials,labsbasedonECOSStudioandICS55PDK

?help200+undergradstotape-outinICS55laterthisyear

?Foracademiaorindividual(2026Q2~Q3)

?supportonlineSoCintegration(poweredbyIPMarket)

?opensourcePLLandDDR3PHYIPonECOSStudio

?allowuserstouploadverifiedEDAalgorithmtoevaluate

?provideflexiblesalesmixes(Independent/Multi-Die)“SoCCanvas”

(SoCdesigncomponentofECOSStudio)

2025/11/21OpenSource@Siemens202521/27

Opensilicondesigncourse(willstartfrom2025.9)

?TeachstudentstocompleteSoC&physicaldesignwithopenEDAinICS55poweredbyECOSStudio

?Fillthegapbetweenacademicandindustry

?Content

?transistorcircuit(gatestructure/simulation)

?SoCdesign/integration/verification(CDC,UVM,STA,TCL,SDC…)

?physicaldesign(wholebackendflow)

?Feature

?Infrastructure(xschem,ngspice,KLayout,Cocotb,pyUVM,Yosys,iEDA,OpenROAD,cloudplatform…)

?establishopen,flexibleandcommunity-driventeaching-learningmode

?tape-outinICS55withiEDAonECOSStudio

?Releasefirstversionin2025Q3

TodayweareHERE!

OpenSiliconDesignCourse–UsingECOSStudio

“OneStudentOneChip”(startfrom2021.6)

?TeachstudentstodesignrealchipsinopenPDK

?Focusonpromotingstudents’professionalabilities

?Content(realfull-stack!)

?HW/SWco-design(APP,simulator,runtime,OS,micro-architecture)

?logical/physicaldesign(formal,synthesis,PPAevaluation,RTL2GDSflow)

?Feature

?Infrastructure(AM,NEMU,CacheSim/BrSim,DiffTest,SDB,SymbiYosys,Yosys,iEDA…)

?extensiveteachingexperience(involved12000+students)

?tape-outforfree!(studentswhopasstheonlineassessment)

?NewversionwithopenEDA&PDKwillreleasein

2025soon

2025/11/21OpenSource@Siemens202522/27

OpenSiliconDesignCourse

?Usingcompleteopen-sourcetoolchain

?xschem,ngspice,Klayout(Transistor)

?cocotb,pyuvm,SymbiYosys(SoC)

?Yosys,OpenROAD,ICS55openPDK(Physicaldesign)

?self-developedtools:HDLVim,teenySoC,ACES,AXLE,iEDA,ECOSStudio(ongoing)…

?

…

?DevelopingLMS-Centricwebsite(serversarelocatedinHongKongSAR)

?haveunifiedIDverificationandmodernUIsystem

?customizeanextensible,robustandeasy-to-useLMSandRewardPointMall

?putallhandout,webinarvideo,slides,tools,contest/marathon…inoneplace!

?Moreopenandprofessionallearningsupport

?encouragerapiddiscussiononWeChat/Discord

?5~10full-timeTAswith6~7volunteers

2025/11/21OpenSource@Siemens202523/27

Post-siliconEducationin2025Q4/2026Q1

?Providepost-siliconeducationinfuture(bonding/packaging,PCB,bring-up,…)

?Shortendevelopmentperiod(SDK,APP,software,productpackaging…)

?solderOSOC3rdchip(110nm)

?6-layersstackdesign(Allegro)

?officiallyreleasein2023.4

?solderOSOC4thchip(28nm)

?8-layersstackdesign(Allegro)

?officiallyreleasein2023.10

What’snext?

1.platformized,componentized

2.encourageMOREstudentsinvolved!

?solderOSOC5thchip(28nm)

?4-8layersstackdesign(KiCad)

?comingsoon!expectedin2025.7

2025/11/21OpenSource@Siemens202524/27

DesignPractices:ACustomizedASICretroSoC

?AnopensourceSoCframework(maybe~5yearsthatallcanbedone)

apertusAXIOMBETACompact

?generatedbyACES(RustSoCbuilder,using“Combo”config)

?provideWiFi,MIPI,ISP,2D/3Dgraphicaccelerator(ongoing)…

?Focusonsomestuff:

?retrogameconsole

?APS-C/full-frameCMOScamera

?

…

?Buildupacommunity-drivendevelopmode

?getinstantfeedbacksinsuperearlystages

?makecontinuedinfluence

?ProvidebaselineforiEDA,AiEDAandopenROAD

?Tape-outarealchipbyusingopenPDK

?long-termproject

?supportedbycommunity(ECOSStudio,TinyTapeout…)

2025/11/21OpenSource@Siemens202525/27

retroSoC:TechnicalRoadmapin2025

MINI

1.RV32I/EC

2.minimumdesign

3.noon-chipSRAM

4.wroteinVerilog

5.10~20Kinstances

6.package:QFN48/64

7.demo:smartband

PRO

1.RV64IMAC

2.high-performance

3.L1/L2Cache

4.wroteinSV

5.50~100Kinstances

6.package:QFP100

7.demo:bootLinux

STD

1.RV32IMAC

2.balancedesign

3.ITCM/DTCM/Cache

4.wroteinSV

5.30~50Kinstances

6.package:QFN88

7.demo:smartwatch

Majormilestone

1.hardendesign(MDD)

2.maintaintheCRT

3.runopenEDACI/CD

4.SoCintegrate,design,verification(keypoint)

5.runcommercialflow

6.writedev./useguide

7.switchtoiterativedev.mode

8.auto-generatedbySoCbuilder(teenySoC)

?AMCU-classRV32IMACSoC(~50Kinstances,demo:smartwatch)(2025Q3)

?AnApplication-classRV64IMACSoC(~100Kinstances,demo:gameconsole)(2025Q4)

1.Low-speedIPs:UART,TIMER,PWM,WDG,RTC,I2C,SPI,PS2,RNG,…

2.MemoryIPs:QPIPSRAM,OPIDDRPSRAM

3.ApplicationIPs:SDIO,DMA,VGA,DVP,USB1.1,I2S,2DGraphicAccel.

2025/11/21OpenSource@Siemens202526/27

retroSoC:MultimediaIPsDevelopmentPlan

?Acommunity-drivenproject(hostedbyOSOCShenzhenBase)

?ledbyinternalspecialR&Dgroup(composedofTAsandinterns)

?developDMA,SDIO,DVP,USB,2DGraphicAccel.etc.

?full-stackdesign(IP,SoC,SW,PCB,Pack.,Docs)

/retroSoC

2025/11/21OpenSource@Siemens202527/27

retroSoC:MultimediaIPsDevelopmentPlan

?PrismGPUproject(

/PrismGPU

)

?anewopen-source3DGPU

?plantosupportFULLOpenGL1.xAPI(MESA)

?firstversionwillbeintegratedintoretroSoCPro

?optimizeforaLinux-capablesingle-core(RV64GC)SoC

?fix-functionpipeline,DMA+AXI+VGAarch.(novideocodecimpl.)

?giveprioritytoadaptingQuake,NeedforSpeedIII:HotPursuit

?tape-outin2025Q4~2026Q1

?collateandopenalllearningmaterials(2026Q2~Q3)

?tape-outforstudentsinStageAorSfromOneStudentOneChip

?designapractice-orientedGPUtutorial

?C