第4章用VHDL程序?qū)崿F(xiàn)常用邏輯電路

4.1組合邏輯電路設(shè)計(jì)

4.1.1基木邏輯門

libraryieee;

useiee.stdjogic_i164.all;

entityjbmis

port(a,b:inbit;

fl,f2,f3.f4,f5,f:oulbil);

endjbm;

architectureaofjbmis

begin

fl<=aandb;-構(gòu)成與門

f2<=aorb：--構(gòu)成或門

f<=nota;--構(gòu)成非門

f3<=anandb;-構(gòu)成與非門

f4<=anorb:一構(gòu)成異或門f5<=nol(a

xorb);-構(gòu)成異或非門即同門

end;

4.1.2三態(tài)門

libraryieee;

useiecc.sid_logic_l164.all;

entitytri_sis

port(enable:instd_logic;

datain:instd_logic_vector(7downto0);

dataout:outstd_logic_vector(7downtoO));

endtri_s;

architecturebhvoftri_sis

begin

process(enable.datain)

begin

ifenable-1'then

dataou?=datain;

else

dataout<="ZZZZZZZZ";

endif;

endprocess:

endbhv;

4.1.33-8譯碼器

libraryieee;

useieee.std_logic_lI64.all;

entitydccodcr3_8is

port(a.b.c.g1,g2a.g2b:instdjogic;

y:outstd_logic_vector(7downto0));

enddecoder3_8:

architectureaofdecoder3_8is

signaldz:std_logic_vector(2downto0);

b，gin

dz<=c&b&a;

process(dz.gI.g2a.g2b)

begin

if(gl='l'andg2a='0'andg2b='0)thcn

casedzis

when"1H"=>y<="OI111111";

whenothers=>y<="XXXXXXXX";

endcase;

else

endif;

endprocess;

4.1.4優(yōu)先編碼器

libraryieee;

useiccc.sid_logic_l164.alI

entitycoderis

port(din:instd_logic_vector(0to7：;

output:outstd_logic_vector(0to2));

endcoder;

architecturebehaveofcoderis

signalsint:std_logic_vevtor(4downtc0);

begin

process(din)

begin

if(din(7)-O')then

output<="000";

elsif(din(6)=,O')then

output<="100";

clsif(din(5)='O')then

output<="010";

elsif(din(4)='O')then

output<="110";

elsif(din(3)-O')then

oulpul<="OOI";

elsif(din(2)='()')then

output<="101";

elsif(din(l)-O')then

output<="OH";

else

output<="111";

endif;

2ndprocess;

endbehav;

4.1.57段碼譯碼器

libraryieee;

useieee.sld_logic_1164.alI

entitydec!7sis

port(a:insld_logic_vector(3downlo0);

led7s:outstd_logic_vector(6downto0));

enddec!7s;

architecturebehaveofdec!7sis

begin

process(a)

begin

caseais

when"0000"=>Ied7s<="0111111"：

when"0001M=>Icd7s<="00C0I10";

when"0010"=>led7s<="1011011"

when"0011"=>lcd7s<="10()11II"

when“0100"=>led7s<="ll(M)IIO"

when"oior,=>Ied7s<="HOI101"

when"0110"=>led7s<="1111101"

when"0111"=>led7s<="0000111"

when“1000"=>led7s<="1111111"

when“1001"=>led7s<="1101III"

when"1010"=>led7s<="I110IH"

when“1011"=>led7s<="11111()0"

when“1100"=>led7s<="0111001"

when"1101"=>led7s<=

when"II10"=>led7s<="1111001"

when"111I"=>Ied7s<="1110001";

whenothers=>null;

endcase;

endprocess;

endbehave;

4.1.6二-十進(jìn)制BCD譯碼器

libraryieee;

useieee.std_logic_l164.all;

useieee.stdjogtc_signed.alk

entitybedyinqis

port(din:inintegerrange15downto0:

a.b:outintegerrange9downto0);

end:

architecturefpqlofbedymqis

begin

pl:proccss(din)

begin

ifdin<10then

a<=din;

b<=0;

else

a<=din-10;

b<=l;

endif;

endprocesspI;

4.1.7多位加(減)法器

libraryieee:

useieee.std_Iogic_l164.all;

useieee.st(l_logic_signed.all;

entityjianfaqiis

port(a,b:instd_logic_vector(0to3);

cO:instd_logic;

cl:outstd_logic;

d:outstd_logic_veclor(0to3));

end;

architcclureaofjianfaqiis

begin

process

begin

il'a>b+cO(hen

d<=a-(b+cO);

cl<='0';

else

endprocess;

enddff_art;

JK觸發(fā)器

libraryieee:

useieee.std_logic_l164.all:

useieee.std_logic_signed.all;

entityasynjkffis

port(j,k.clk.set.reset:instd」ogic;

q.qb:outstd」ogic);

endasynjkff;

architecturejkfflartofasynjkffis

singalq_s,qb_s:std_logic;

begin

pr<>cess(clk,set,rcscl)

begin

if(set-0'andreset-1")then

q_s<=T;

qb_s<='0';

elsif(set=Tandreset='O')then

q_s<='0';

qb_s<-1,;

elsif(clk'eventandelk-I')then

if(j='O'andk-1')then

q_s<='0';

qb_s<=T;

elsifandk='O')then

q-s<-r；

qb_s<='0';

elsif(j-Tandk='1')then

q_s<=nolq_s;

qb_s<=notqb_s;

endif;

endif;

q<=q_s:

qb<=qb_s;

endprocess;

endjkfLart;

T觸發(fā)器

libraryieee;

useieee.std_logic_l164.all;

useiccc.std_logic_signcd.all;

entitytffis

port(t,clk:instdjogic;

q:outstdjogic);

end;

architecturetff_artofiffis

signalq_temp:sld_logic;

begin

pl:process(clk)

begin

ifrising_edge(clk)then

ift=rthen-當(dāng)T=l時(shí)T觸發(fā)器具有2分頻的功能

q_temp<=notq_temp;

else

qtemp<=qtemp;

endif;

endif;

q<=q_temp;

endprocess;

q<=q_temp;

endtff_art；

422計(jì)數(shù)器

libraryiccc;

useieee.std_logic_lI64.alk

useieee.std_logic_unsigned.all;

entitycnt4IS

port(elk:instd_logic;

q:outstd_logic_vcclor(3downto0));

endcnt4;

architecturebehaveofcnt4is

signalqI:std_logic_vector(3downto0);

begin

processedk)

begin

if(clk'eventandelk='I')then

ql<=q1+1;

endif;

endprocess;

q<=ql;

endbehave;

一般計(jì)數(shù)器設(shè)計(jì)

libraryiccc;

useieee.stdjogic_l164.all;

useieee.std_logic_unsigned.all;

entityent10is

port(clk,rst,en,updown:instdjogic;

cq:outsid」ogic_vecior(3downto0));

endcnllO;

architecturebehaveofent10is

氏gin

proccss(clk,rst,cn,up<lown)

variablecqi:std_logic_vector(3downto0);

begin

ifrst='rthen

cqi:=(others=>'0');--計(jì)數(shù)器異步復(fù)位

elsif(clk'eventandelk=*1')then--檢測(cè)時(shí)鐘上升沿

ifen-i'then--檢測(cè)是否允許計(jì)數(shù)（同步使能）

ifupdown='0'then

ifcqi<9then

cqi:=cqi+l;-允許計(jì)數(shù).檢測(cè)是否小于9

else

cqi:=(others=>'0');一大于9,計(jì)數(shù)值清零

endif;

else

ifcqi>()then

cqi:=cqi-1;一檢測(cè)是否大于0

else

cqi:=(others=>'r);一否則，計(jì)數(shù)值置I

endif;

endif;

endif;

endif;

cq<=cqi;--將計(jì)數(shù)值向端口輸出

endprocess;

endbehave;

4.2.3分頻器

libraryieee:

usestd_logic_lI64.all;

ussstd_logic_unsigned.all:

entityfreqlis

port(clk:insld」ogic:

d:instd_logic_vector(7downto0);

font:outstdjogic);

end;

architectureoneofdvfis

signalfull:stdjogic;

begin

p_reg:process(clk)

variablecnt8:std_logic_vector(7downto0);

begin

ifclk'cvcntandclk="1'then--檢測(cè)時(shí)鐘上升沿

ifcnt8=""then

cnt8:=d:--當(dāng)CNT8計(jì)數(shù)計(jì)滿時(shí)，輸入數(shù)據(jù)D被同步預(yù)苣給計(jì)數(shù)器CNT8

-同時(shí)使溢出標(biāo)志信號(hào)FULL輸出為高電平

else

cnt8:=cnt8+l;-否則繼續(xù)作加1計(jì)數(shù)

fulK='O';-且輸出溢出標(biāo)志信號(hào)FULL為低電平

endif:

endif;

endprocessp_reg;

p_div:process(full)

variablecnt2:stdjogic;

begin

iffulKcvcntandfull='i'then

cnt2:=notcnt2;-如果溢出標(biāo)志信號(hào)FULL為高電平，T觸發(fā)器輸出取反

ifcnt2=,rthen

fout<-r；

else

fout<='0';

endif;

endif;

endprocessp_div;

end:

4.2.4移位寄存器

libraryieee;

useieee.std_logic_lI64.all:

entityshiftis

port(c!k.cO:instdjogic;--時(shí)鐘和進(jìn)位輸入

md:instd_logic_vector(2downto0);--移位模式控制字d:

instd_logic_vector(7downto0);一待加載移位的數(shù)據(jù)qb:

outsld_logic_vector(7downto0);--移位數(shù)據(jù)輸出cn:out

stdjogic);一進(jìn)位輸出

end;

a-chiteciurebehaveofshiftis

signalreg:std_logic_vcc(or(7downto0);

signalcy:std_logic;

begin

process(clk,md,cO)

begin

ifclk'eventandelk-I'then

casemdis

when"0()1"=>reg(0)<=cO;

reg(7downto1)<=reg16downto0);

cy<=reg(7);-帶進(jìn)位循環(huán)左移

when"010"=>reg(0)<=reg(7);

reg(7downtoI)<=reg(6downto0)；--自循環(huán)左移

when"011"=>reg(7)<=reg(O);

reg(6downto0)<=regi7downto1);-自循環(huán)右移

when"100"=>reg(7)<=C0;

reg(6downto0)v=regi7downto1);

cy<=reg(0);--帶進(jìn)位循環(huán)右移

when"101"=>reg(7downto0)<=d(7downto0);--加載恃移數(shù)

whenothers=>reg<=reg;cy<=cy;??保持

endcase;

endif:

2ndprocess;

qb(7downto0)<=reg(7downto0);cn<=cy;--移位后渝出

endbchav;

4.3狀態(tài)機(jī)邏輯電路設(shè)計(jì)

4.3.1一般狀態(tài)機(jī)設(shè)計(jì)

libraryicec;

useieee.stdjogic_l164.all;

entitys_machineis

port(elk,reset:insid」ogic;

state_inputs:instd_logic_vector(0tol);

coinb_outputs:outintegerrange0to15);

ends_machine:

architecturebehvofs_machineis

typefsm_stis(sO,si,s2,s3);-數(shù)據(jù)類型定義，狀態(tài)符號(hào)化

signalcurrenl_slate,nex(_state:fsm_st;-將現(xiàn)態(tài)和次態(tài)定義為新的數(shù)據(jù)類型

b陪iu

reg:process(reset,clk)--主控時(shí)序進(jìn)程

begin

ifreset='1'then

current_state<=sO;-檢測(cè)異步復(fù)位信號(hào)

elsifelk-!'andclk'eventthen

current_state<=next_state;

endif;

endprocess;

com:process(current_state,statejnputs)--主控組合進(jìn)程

begin

casecurrcnl_siatcis

whensO=>comb_outputs<=5;

ifstate_inputs="00"then

next_state<=sO;

else

nexl_state<=sl;

endif;

whensi=>comb_outputs<=8;

ifstatejnputs="00"then

nexl_state<=sl;

else

next_state<=s2;

endif;

whens2=>comb_outputs<=12;

ifsla(c_inputs="11"ikcn

next_state<=sO;

else

next_state<=s3;

endif;

whens3=>comb_outputs<=14;

ifstate_inputs="11"then

next_state<=s3;

else

next_statc<=sO;

endif;

endcase：

endprocess;

endbchv;

4.3.2狀態(tài)機(jī)的應(yīng)用

libraryieee;

useiccc.std_logic_i164.all;

entityasmjedis

port(clk.clr:instd」ogic;

Iedl,led2,led3:outstd_logic);

end;

architectureaofasm_ledis

typestatesis(s0,sl.s2,s3,s4,s5);-對(duì)狀態(tài)機(jī)的狀態(tài)聲明

signalq:std_logic_vector(0to2);

signalstate:states;

b2gin

pl:process(clk,clr)

begin

if(clr='O')then

sta(e<=sO;

clsif(clk'cvenlandelk-I')then

casestateis

whens0=>state<=sI;

whensl=>state<=s2;

whens2=>state<=s3;

whens3=>state<=s4;

whens4=>state<=s5;

whens5=>state<=s0;

whenothers=>s(ale<=sO;

endcase;

endif;

endprocessp1;

p2:process(clr,state)

begin

if(clr='O')then

led1<='O';

led2<='0';

led3<='0';

else

casestaleis

whens0=>ledI<='1';lcd2<-0';lcd3<='0';

whensl=>ledI<='0';led2<='I';]ed3<='0';

whens2=>ledI<='0':led2<='1';led3<='0';

whens3=>led1<='0';led2<=,0,;led3<=,1

when$4=>ledI<='0';lcd2<-O';lcd3<-1

whens5=>ledI<='0';led2<-O';led3<='1

whenothers=>null;

endcase;

endif;

endprocessp2;

end;

第6章EDA仿真技術(shù)應(yīng)用實(shí)例

6.1帶使能和片選端的16：4線優(yōu)先編碼器設(shè)計(jì)

子模塊設(shè)計(jì)源代碼：

libraryiece;

useieee.std_logic_l164.all;

entitypencoderis

port(d:instd_logic_vector(7dowrto0);

ei:instd_logic;-ei:enableinput

gs,eo:oulbit;-gs:chipselectoulput;eo:enahleoutput

q2,q1,qO:outstdjogic);

endpencoden

architectureencoderofpencoderis

b2gin

processed)

begin

if(d(O)='O'andei='0')then

q2<=T;ql<=T;qO<=T;

gs<='0'；co<='r；

elsif(d(l)='O'andei='0')then

q2<=T;ql<=T;q0<='D';

gs<='0';eo<-1';

elsif(d(2)='0'andei='0')then

q2<=,r；ql<='0':q0<='r；

gs<='0';eo<-1';

elsif(d(3)='O'andei='0')then

q2<=,r；ql<='0,;q0<=,9,;

gs<='0';eo<-1';

elsif(d(4)='O'andei-0")then

q2<='0';qlv=T;q0<=T;

gs<='0';eo<='r；

elsif(d(5)='O'andei='0')then

q2<='0';ql<=,r；q0<=,0,;

gs<='0';eo<='r；

elsif(d(6)='0'andei='0')then

q2<='0';ql<=,0,;q0<='l';

gs<='0';eo<='l';

elsif(d(7)='0'andei='0')then-<J7priotyencoder

q2v='0';ql<='0';q(X='C;

gs<='0':eo<='l,;

clsif(ci='r)then

q2v=T;ql<=O;q0v=T;

gs<-r；eo<-r；

'O')then

q2<=T;q1<=T;q0<=T;

gs<-i';co<='0';

endif;

endprocess;

endencoder;

6.27段顯示譯碼器設(shè)計(jì)

譯碼器設(shè)計(jì)源代碼：

libraryieee;

useieee.std_logic_lI64.all:

entitydecoder47is

pjrt(h,ibr,ib_ybr:inbit;

a:insld_logic_vector(3downto0):

y:outstd_logic_vector(6downto0));

enddecoder47;

architectureartofdecoder47is

begin

process(lt,ibr.ib_ybr,a)

variables:std_logic_vector(3downto0);

begin

s:=a(3)&a(2)&a(1)&a(0);

iflt='O'andib_ybr='11then

y<="1111111"；-檢查七段顯示管是否正常

clsifibr='O'anda="0000"thcr

y<=',0000000,1;

else

casesis

when"0000"=>y<="l.llil0";-7E

when"0001"=>y<="0110000";-3()

when"0010"=>y<="1.01101";-6D

whcn"0011"=>y<="011001-79

when"0100"=>y<="0：10011";-33

when"0101"=>y<=,r1011011";-5B

when,0110'=>y<=00Hill";-5F

when"011l"=>y<="l110000";-70

whcn"l000"=>y<="11111ir,;-7E

whcn"l001"=>y<="l：10011";-7B

when"l010"=>y<="0001101";-0D

when"101lM=>y<="0011(X)1";-19

when"ll00"=>y<="0：000ll";-23

when"1101"=>y<="10010H";-4B

when"1110"=>y<="0001111";-OF

when"l11lM=>y<="0000000";

endcase;

endif;

endprocess;

sndart;

6.3帶異步清零端的12位二進(jìn)制全加器設(shè)計(jì)

子模塊源代碼：

libraryiece;

useieee.std_logic_l164.all;

useieee.std_logic_unsigned.all;

entityadder4bis

port(clr,cin:instd_logic;

a,b:instd_logic_vector(3downto0);

s:outstd_logic_vector(3Jownto0);

cout:outstdjogic);

endadder4b;

architectureartofadder4bis

signalsint:std_logic_vector(4downto0);

signalaa,bb:sld_logic_vector(4downto0);

氏gin

process(clr)

begin

ifclr='1'then

sint<="00000";

else

aa<='O'&a;

bb<='O'&b;

sint<=aa+bb+cin;

endif;

s<=sint(3downto0);

cout<=sint(4);

endprocess;

endart;

頂層模塊設(shè)計(jì)源代碼：

libraryieee;

useieee.std_logic_l164.all:

useieee.std_logic_unsigned.all;

entityudder12bis

port(clr.cin:instdjogic;

a.b:instd_logic_vector(11downto0);

s:outstd」ogic_vecior(11downto0);

cout:outstd_logic);

endadder12b;

architectureartofadder12bis

componentadder4bis

port(clr,cin:instdjogic;

a,b:instd_logic_vector(3downto0);

s:outstd_logic_vcctor(3downto0);

cout:outstdjogic);

endcomponent;

signalcarr>_out1:std_logic;

signalcarry_out2:std」ogic;

bigin

u1:adder4bportmap(clr=>clr,cin=>cin,a=>a(3downto0),b=>b(3downto0),

s=>s(3downtoO),coul=>carry_out1);

u2:adder4bportniap(clr=>clr,cin=>carr)f_out1.a=>a(7downto4).b=>b(7downto4),

s=>s(7downto4),cout=>carry_out2);

u3:adder4bpor【map(clr=>cir.cin=>carry_out2.a=>a(11downto8).b=>b(l1downto8).

s=>s(11downto8).cout=>cout):

endart;

6.4帶異步清零/置位端的JK觸發(fā)器設(shè)計(jì)

營(yíng)異步清零/置位端的JK觸發(fā)器源程序如下：

libraryieee;

useieee.std_logic_l164.all;

entityjkffjogicis

p3rt(j.k.clk.clr,set:instdjogic;

q:oulsid」ogic);

cndjkffjogic;

architectureartofjkff_logicis

signalq_s:std_logic;

begin

proccss(clk,clr,sct,j,k)

begin

ifset-0*then

q_s<-1,;一異步置位

elsifclr-1'then

q<='0';?■異步復(fù)位

elsifclk'eventandclk-1'then

if(j-0')and(k='l')then

q_s<-'0';

elsif(j='r)and(k='0')then

q-s<-r；

elsif(j='r)and(k='l')then

q_s<=notq_s;

endif;

endif;

q<=q-s;

endprocess;

endart;

6.54位鎖存器設(shè)計(jì)

子模塊設(shè)計(jì)源代碼：

libraryieee;

useieee.std_logic_lI64.all;

entitylatchlbis

pjrt(d:instdjogic;

ena:instd_logic;一使能端

q:outsidjogic);

endlatch1b;

architectureartoflatch1bis

begin

process(d.ena)

begin

ifena-1'then

q<=d;

endif;

endprocess;

endart;

元件聲明程序包設(shè)計(jì)源代碼：

libraryieee;

useieee.std_logic_lI64.a)l:

packagemy_packageis

componentlatch1

port(d:instdjogic;

enazinstd」ogic;

q:outstdjogic);

endcomponent;

end;

頂層模塊設(shè)計(jì)源代碼：

libraryieee;

useieee.std_logic_l164.all:

usework.my_package.all;-使用用戶自定義的程序包

entitylatch4<iis

pDrt(d:instd_logic_vector(3downto0);

oen:inbit;

q:outstdjogic_vector(3downto0));

endIatch4d：

architectureoneoflatch4dis

signalsig_save:std_iogic_vector(3downto0);

b2gin

getlatch:fornin0to3generate--用for_generate語(yǔ)句循環(huán)例化4個(gè)l位鎖存器

latchx:latchlportmap(d(n),g.sig_save(n));--關(guān)聯(lián)

endgenerate;

q<=sig_savewhenoen='0'

else

"ZZZZ";

endone;

6.632進(jìn)制多樣型計(jì)數(shù)器設(shè)計(jì)

(1)32進(jìn)制同步加法計(jì)數(shù)器源程序

32進(jìn)制同步加法計(jì)數(shù)器源程序如下：

libraryieee:

useieee.std_logic_lI64.all;

useieee.std_logic_unsigned.all;

entitycountcr_plusis

pjrt(clk,clr:instd」ogic;

doutO.dout1:outstd_logic_vector(3downto0));

end;

architectureartofcounter_plusis

signaldO.dl:std_logic_vector(3downto0);--dO代表個(gè)位，dl代表十位

begin

process(clk.clr.)

begin

ifclr='1"then

d1<=(others=>'0');d0<="000C";--同步清零

elsifclk'eventandclk-1'then

if(dI=3andd0=1)then

dl<="0000";

d0<="0000";-計(jì)數(shù)到32時(shí)清零

elsif(dO=l)then

d0<="0000";

dI<=d1+1;

else

dO<=dO+1;

endif;

endif;

dout1<=d1;doutO<=dO;

endprocess;

endart;

(2)32進(jìn)制同步減法計(jì)數(shù)器源程序

32進(jìn)制同步減法計(jì)數(shù)器源程序如下：

libraryiece;

useieee.std」ogic_l164.all;

useieee.std_logic_unsigned.all;

entitycounter_subis

port(clk,clr:instd_logic;

doutO.dout1:outstd_iogic_vector(3downto0));

end;

architectureartofcounter_subis

signaldO,dl:std_logic_vcctor(3downto0);-dO代表個(gè)位，dl代表十位

begin

process(clk,cIr)

begin

ifclr='1'then

dI<="0000";d0<="0000";--異步清零

elsifclk'eventandclk-1'then

if(d1=0andd0=0)then

dl<="00U";d0<="0001";一設(shè)定容量31

elsif(dO=O)then

d0<="0001,,;dl<=dl-l;

else

dO<=dO-l;dl<=dl;

endif;

endif;

dout1<=d1;doutO<=dO;

endprocess;

endart:

(3)32進(jìn)制同步可逆計(jì)數(shù)器源程序

32進(jìn)制同步可逆計(jì)數(shù)器源程目如下：

libraryiccc;

useieee.std_iogic_l164.all;

useieee.std_iogic_unsigned.all;

entitycoiinter_reversibleis

p3rt(clk.clr,s:instd_logic;-s=l加法計(jì)數(shù)，s=3減法計(jì)數(shù)

doutO,dout1:outstd_logic_vector(3downto0));

end;

architectureartofcounter_reversibleis

signaldO,d1:std_logic_vector(3downto0);--dO代表個(gè)位，dl代表十位

b2gin

process(clk,clr,s)

begin

ifclr='l'then

dl<="0000";d(X="0000";--異步清零

elsif(clk'evcntandclk-11)then

ifs-1'then

if(dl=3andd0=1)then

di<="0(X)0";

d0<="0000";一計(jì)數(shù)到31時(shí)清零

elsif(dO=1)then

d0<="0000";

dl<=dl+l;

elsed(X=dO+1;

endif;

clsifs='O'then

if(dl=OanddO=O)then

dl<="00H";

110<="0001";??設(shè)定容量31

elsif(dO=O)then

d0<="000l";

dl<=dl-l;

else

dO<=dO-1;

dl<=dl;

endif;

endif;

endif;

dout1<=d1;doulO<=dO;

andprocess;

endart;

(4)32進(jìn)制異步加法計(jì)數(shù)器源程序

32進(jìn)制異步加法計(jì)數(shù)器源程序如下:

。子模塊D觸發(fā)器源程序設(shè)計(jì)，

libraryieee:

useieee.std_logic_l164.all;

entitydffris

port(clk,clr,d:instd_Iogic;

q,qb:outsldjogic);

end;

architectureartofdffris

signalqin:std_logic:

begin

q<=qin;

qb<=nolqin;

process(clk.clr)

begin

ifclr='l'(hen

qin<='0';

elsif(clk'eventandelk-l')then

qin<=d;

endif;

endprocess;

endart;

②頂層異步加法計(jì)數(shù)器源程序設(shè)計(jì)。

libraryieee;

IBCicce.std_logic_l164.all;

entitycounter_ais一異步加法計(jì)數(shù)器

part(clk,clr:instd_logic;

count:outstd_logic_vector(4downto0));

end;

architectureartofcounter_ais

signalcount_in:std_logic_vector(5downto0);

componentdffrport(clr.clk.d:instd_logic;