1、1,Digital Logic Design and ApplicatonLecture #17,Latches and Flip-Flops,UESTC, Spring 2013,2,再談串行輸入加法器的實(shí)現(xiàn),CLK,電平有效還是邊沿有效？,串行輸入、串行輸出 注意：時(shí)鐘同步,Iterative Vs. Sequential,3,Iterative Versus Sequential Circuits,C0,C4,X0 Y0,X1 Y1,X2 Y2,X3 Y3,S0,S1,S2,S3,4,7.2 Latches and Flip-Flops,Latches change its output

2、s at any time (enable input is asserted). Flip-Flops change its outputs only when the clock changes,Positive-Edge Rising-Edge,Negative-dge Falling-Edge,Level triggered,Edge-triggered, ET,5,7.2.5 Edge-Triggered D Flip-Flops,When CLK=0,When CLK=1,Qm follows D; Q is unchanging.,Qm is unchanging, Q = Qm

3、 until the next rising CLK edge,1. Master/Slave, Positive-edge-triggered,Q changes only when CLK rises from 0 to 1,6,Timing Diagram for master-slave D F/F,Q =D( ),7,8,D Latch,D Flip-Flop edge-triggered,when CLK is asserted,對(duì)信號(hào)擾動(dòng)不敏感,受信號(hào)擾動(dòng)影響,9,D flip-flop timing parameters,Propagation delay ( from CLK

4、 ),Setup time ( D before CLK） Hold time ( D after CLK),D,CLK,Q,在時(shí)鐘上升邊沿附近有一個(gè)時(shí)間窗口，在此窗口時(shí)間內(nèi)，數(shù)據(jù)輸入D不能改變，否則電路進(jìn)入亞穩(wěn)態(tài)。,從輸入信號(hào)D到來時(shí)刻至信號(hào)D 達(dá)到穩(wěn)定所持續(xù)的時(shí)間。,從輸入信號(hào)D達(dá)到穩(wěn)定至信號(hào)D 被鎖存器接受所持續(xù)的時(shí)間。,10,2. Negative-Edge-Trigged D Flip-Flop,3. D Flip-Flop with preset and clear,同步(synchronous)是指與時(shí)鐘同步，即時(shí)鐘觸發(fā)條件滿足時(shí)檢測(cè)清零(置位)信號(hào)是否有效，有效則在下一個(gè)時(shí)間周

5、期的觸發(fā)條件下，執(zhí)行清零(置位)； 異步(asynchronous)是清零(置位)信號(hào)有效時(shí)，無視觸發(fā)脈沖，立即清零(置位)。,11,12,3. D Flip-Flop with preset and clear,asynchronous inputs behavior like the set and reset inputs on S-R latch.,1,0,0,1,1,1,1,1,0,1,1,13,Timing Diagram for D flip-flop with preset and clear,3. D Flip-Flop with preset and clear,synch

6、ronous inputs: PR(preset) and CLR(clear depend on the CLK,14,Reset,CLK,?,R有效，Q=0 R無效，Q=Din,15,4. Commercial TTL D Flip-Flops (74LS74),P535 Figure 7-20,PR_L,CLR_L,CLK,D,Q,QN,維持阻塞結(jié)構(gòu),Smaller and faster,16,5. CMOS edge-triggered D circuit,Uses transmission gates in feedback loops,Q,D,CLK,D,CLK,Two feedb

7、ack loops (master and slave latches),17,7.2.6 D Flip-Flop with Enable,If EN is asserted, the external D input is selected; if EN is negated, the current output is used.,18,7.2.7 Scan Flip-Flop,TE=0, D is selected TE=1, TI is selected,19,TO,TI,CLK,TE,When TE is negated, Q = D,20,7.2.8 Master/Slave S-

8、R Flip-Flop,21,Master/Slave S-R Flip-Flop Timing Diagram,暫時(shí)忽略延遲時(shí)間等動(dòng)態(tài)特性,C,unpredictable,unpredictable,22,C,Edge-Triggered?,unpredictable,The S-R flip-flop changes its outputs only at the falling edge of C.,But it is not truly edge triggered.,Pulse-Triggered flip-flops,23,7.2.8 Master/Slave S-R Flip-F

9、lop,postponed-output indicator,dynamic input indicator edge triggered,24,7.2.9 Master/Slave J-K Flip-Flop,消除主從S-R觸發(fā)器存在的約束條件,利用反饋消除主從S-R觸發(fā)器存在的約束條件,S = JQ R = KQ meet SR=0,J-K FF Characteristic Equation,Q* = JQ + (KQ)Q,(K+Q)Q,KQ,25,7.2.10 Edge-Triggered J-K Flip-Flop,J-K FF: Q* = JQ + KQ,D FF: Q* = D,

10、26,7.2.11 T Flip-Flop,A T flip-flop changes state on every tick of the clock.,27,Design a T Flip-Flop,Using a D flip-flop D FF: Q* = D T FF: Q* = Q D = Q,Using a J-K flip-flop JK: Q* = JQ + KQ T: Q* = Q J = K = 1,28,T Flip-Flop with Enable,T：Q* = ENQ + ENQ,JK：Q* = JQ + KQ,D：Q* = D,29,7.2.11 T Flip-Flop,說明： 傳統(tǒng)中文教材中認(rèn)為： T 觸發(fā)器的特征方程 Q* = TQ + TQ T=1時(shí)翻轉(zhuǎn)；T=0時(shí)維持,30,關(guān)于電路結(jié)構(gòu)和邏輯功能,同一功能的觸發(fā)器可用不同電路結(jié)構(gòu)實(shí)現(xiàn) 主從結(jié)構(gòu)的D觸發(fā)器、維持阻塞結(jié)構(gòu)的D觸發(fā)器 同類電路結(jié)構(gòu)可做成不同功能的觸發(fā)器 維持阻塞結(jié)構(gòu)的：D觸發(fā)器、J-K觸發(fā)器,31,Summaries of Latch and Flip-Flop,Latch: output changes when CLK is asserted Flip-Flop: outpu