1、程序：(1)時基分頻模塊的VHDL源程序（CB10.VHD)LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY CB10 IS PORT(CLK:IN STD_LOGIC; 輸入時鐘信號 CO:OUT STD_LOGIC); 分頻輸出信號END CB10; 實體描述ARCHITECTURE ART OF CB10 IS 結(jié)構(gòu)體描述 SIGNAL COUNT:STD_LOGIC_VECTOR(3 DOWNTO 0); 硬件系統(tǒng)的基本數(shù)據(jù)對象 BEGIN PROCESS(CLK) 進程敏感信

2、號 BEGIN IF RISING_EDGE(CLK)THEN IF COUNT=1001THEN COUNT=0000; CO=1; ELSE COUNT=COUNT+1; COEN=0; 選中狀態(tài)為S0、EN=0 IF SP=1THEN NEXT_STATE=S1; ELSE NEXT_STATEEN=1; 選中狀態(tài)為S1、EN=1 IF SP=1THEN NEXT_STATE=S1; ELSE NEXT_STATEEN=1; 選中狀態(tài)為S2、EN=1 IF SP=1THEN NEXT_STATE=S3; ELSE NEXT_STATEEN=0; 選中狀態(tài)為S3、EN=0 IF SP=1T

3、HEN NEXT_STATE=S3; ELSE NEXT_STATE=S0; END IF; END CASE; END PROCESS; SYNCH:PROCESS(CLK) 時序進程 BEGIN IF CLR=1THEN CURRENT_STATE=S0; ELSIF CLKEVENT AND CLK=1THEN CURRENT_STATE=NEXT_STATE; END IF; END PROCESS;END BEHAVE;（3）計時模塊的VHDL源程序十進制計數(shù)器的VHDL源程序cdu10.vhdLIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE

4、IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY cdu10 ISPORT(CLK:IN STD_LOGIC; 時鐘信號 CLR:IN STD_LOGIC; 清零信號 EN:IN STD_LOGIC; 計數(shù)使能信號 CN:OUT STD_LOGIC; 計數(shù)輸出信號 COUNT10:OUT STD_LOGIC_VECTOR(3 DOWNTO 0); 計數(shù)值END cdu10;ARCHITECTURE ART OF cdu10 ISSIGNAL SCOUNT10:STD_LOGIC_VECTOR(3 DOWNTO 0);BEGINCOUNT10 = SCOUNT10;PROCE

5、SS(CLK,CLR,EN)BEGINIF (CLR=1)THENSCOUNT10 = 0000;CN = 0;ELSIF RISING_EDGE(CLK) THEN 脈沖為上跳沿觸發(fā)IF(EN=1) THEN IF SCOUNT10=1001THENCN = 1;SCOUNT10 = 0000;ELSECN = 0;SCOUNT10 = SCOUNT10+1;END IF;END IF;END IF;END PROCESS;END ART;六進制計數(shù)器的VHDL源程序cdu6.vhdLIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_L

6、OGIC_UNSIGNED.ALL;ENTITY cdu6 ISPORT(CLK:IN STD_LOGIC; CLR:IN STD_LOGIC; EN:IN STD_LOGIC; CN:OUT STD_LOGIC; 計數(shù)輸出信號 COUNT6:OUT STD_LOGIC_VECTOR(3 DOWNTO 0); 計數(shù)值END cdu6;ARCHITECTURE ART OF cdu6 ISSIGNAL SCOUNT6:STD_LOGIC_VECTOR(3 DOWNTO 0);BEGINCOUNT6 = SCOUNT6;PROCESS(CLK,CLR,EN)BEGINIF (CLR=1)THENS

7、COUNT6 = 0000;CN = 0;ELSIF RISING_EDGE(CLK) THENIF(EN=1) THEN IF SCOUNT6=0101THENCN = 1;SCOUNT6 = 0000;ELSECN = 0;SCOUNT6 = SCOUNT6+1;END IF;END IF;END IF;END PROCESS;END ART;計時器的VHDL源程序count.vhdLIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY count ISPORT(CLK:IN STD_LOGIC; CLR:IN STD_LOGIC; EN:IN ST

8、D_LOGIC; S_1MS: OUT STD_LOGIC_VECTOR(3 DOWNTO 0); 毫秒計數(shù)值 S_10MS: OUT STD_LOGIC_VECTOR(3 DOWNTO 0); 十毫秒計數(shù)值 S_100MS: OUT STD_LOGIC_VECTOR(3 DOWNTO 0); 百毫秒計數(shù)值 S_1S: OUT STD_LOGIC_VECTOR(3 DOWNTO 0); 秒計數(shù)值 S_10S: OUT STD_LOGIC_VECTOR(3 DOWNTO 0); 十秒計數(shù)值 M_1MIN: OUT STD_LOGIC_VECTOR(3 DOWNTO 0); 分計數(shù)值 M_10MI

9、N: OUT STD_LOGIC_VECTOR(3 DOWNTO 0); 十分計數(shù)值 HOUR: OUT STD_LOGIC_VECTOR(3 DOWNTO 0); 小時計數(shù)值END count ;ARCHITECTURE ART OF count IS COMPONENT cdu10 元件例化PORT(CLK:IN STD_LOGIC; CLR:IN STD_LOGIC; EN:IN STD_LOGIC; CN:OUT STD_LOGIC; COUNT10:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);END COMPONENT cdu10;COMPONENT cdu6

10、元件例化PORT(CLK:IN STD_LOGIC; CLR:IN STD_LOGIC; EN:IN STD_LOGIC; CN:OUT STD_LOGIC; COUNT6:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);END COMPONENT cdu6;SIGNAL A,B,C,D,E,F,G,H:STD_LOGIC;BEGINU1:cdu10 PORT MAP(CLK,CLR,EN,A,S_1MS);U2:cdu10 PORT MAP(A,CLR,EN,B,S_10MS);U3:cdu10 PORT MAP(B,CLR,EN,C,S_100MS);U4:cdu10 P

11、ORT MAP(C,CLR,EN,D,S_1S);U5:cdu6 PORT MAP(D,CLR,EN,E,S_10S);U6:cdu10 PORT MAP(E,CLR,EN,F,M_1MIN);U7:cdu6 PORT MAP(F,CLR,EN,G,M_10MIN);U8:cdu10 PORT MAP(G,CLR,EN,H,HOUR);END ART;（4）顯示模塊的VHDL源程序數(shù)據(jù)選擇器的VHDL源程序（MULX.VHD)LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY MULX

12、IS PORT(CLK,CLR,EN:IN STD_LOGIC; S_1MS: IN STD_LOGIC_VECTOR(3 DOWNTO 0); 毫秒計數(shù)器 S_10MS: IN STD_LOGIC_VECTOR(3 DOWNTO 0); 十毫秒計數(shù)器 S_100MS: IN STD_LOGIC_VECTOR(3 DOWNTO 0); 百毫秒計數(shù)器 S_1S: IN STD_LOGIC_VECTOR(3 DOWNTO 0); 秒計數(shù)器 S_10S: IN STD_LOGIC_VECTOR(3 DOWNTO 0); 十秒計數(shù)器 M_1MIN: IN STD_LOGIC_VECTOR(3 DOWN

13、TO 0); 分計數(shù)器 M_10MIN: IN STD_LOGIC_VECTOR(3 DOWNTO 0); 十分計數(shù)器 HOUR: IN STD_LOGIC_VECTOR(3 DOWNTO 0); 小時計數(shù)器 OUTBCD: OUT STD_LOGIC_VECTOR(3 DOWNTO 0); BCD碼輸出 SEG: OUT STD_LOGIC_VECTOR(7 DOWNTO 0); 七段譯碼輸出END MULX;ARCHITECTURE ART OF MULX IS SIGNAL COUNT:STD_LOGIC_VECTOR(3 DOWNTO 0); BEGIN PROCESS(CLK) BE

14、GIN IF CLR=1THEN COUNT=1111; ELSIF RISING_EDGE(CLK)THEN IF EN=1THEN IF COUNT=1001THEN COUNT=0000; ELSE COUNTOUTBCD=S_1MS; SEGOUTBCD=S_10MS; SEGOUTBCD=S_100MS; SEGOUTBCD=S_1S; SEGOUTBCD=S_10S; SEGOUTBCD=M_1MIN; SEGOUTBCD=M_10MIN; SEGOUTBCD=HOUR; SEGOUTBCD=S_1MS; SEGOUTBCD=S_10MS; SEGOUTBCD=0000; SEG=

15、00000000; END CASE; END IF; END PROCESS;END ART;BCD七段譯碼驅(qū)動器的VHDL源程序(BCD.VHD)LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY BCD7 ISPORT(BCD:IN STD_LOGIC_VECTOR(3 DOWNTO 0); 輸入為4位二進制數(shù)，范圍從0到9 LED:OUT STD_LOGIC_VECTOR(6 DOWNTO 0); 7段譯碼輸出END BCD7;ARCHITECTURE ART OF BCD7 I

16、S BEGIN LED=1111110WHEN BCD=0000ELSE 0的7段譯碼（以下類推） 0110000WHEN BCD=0001ELSE 1101101WHEN BCD=0010ELSE 1111001WHEN BCD=0011ELSE 0110011WHEN BCD=0100ELSE 1011011WHEN BCD=0101ELSE 1011111WHEN BCD=0110ELSE 1110000WHEN BCD=1000ELSE 1111011WHEN BCD=1001ELSE 0000000; 其他情況的輸出END ART;（5）頂層設(shè)計的的VHDL源程序(mb.vhd)LI

17、BRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY mb ISPORT(SP:IN STD_LOGIC; CLR:IN STD_LOGIC; CLK:IN STD_LOGIC; CO:OUT STD_LOGIC; EN:OUT STD_LOGIC; LED:OUT STD_LOGIC_VECTOR(6 DOWNTO 0); OUTBCD:OUT STD_LOGIC_VECTOR(3 DOWNTO 0); SEG:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);END mb;ARCHITECTURE ART OF mb ISCOMPONE

18、NT CTRLPORT(SP:IN STD_LOGIC; CLR:IN STD_LOGIC; CLK:IN STD_LOGIC; EN:OUT STD_LOGIC);END COMPONENT;COMPONENT CB10PORT(CLK:IN STD_LOGIC; CO:OUT STD_LOGIC);END COMPONENT;COMPONENT countPORT(CLK:IN STD_LOGIC; CLR:IN STD_LOGIC; EN:IN STD_LOGIC; S_1MS: OUT STD_LOGIC_VECTOR(3 DOWNTO 0); S_10MS: OUT STD_LOGI

19、C_VECTOR(3 DOWNTO 0); S_100MS: OUT STD_LOGIC_VECTOR(3 DOWNTO 0); S_1S: OUT STD_LOGIC_VECTOR(3 DOWNTO 0); S_10S: OUT STD_LOGIC_VECTOR(3 DOWNTO 0); M_1MIN: OUT STD_LOGIC_VECTOR(3 DOWNTO 0); M_10MIN: OUT STD_LOGIC_VECTOR(3 DOWNTO 0); HOUR: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);END COMPONENT ;COMPONENT BCD7P

20、ORT(BCD:IN STD_LOGIC_VECTOR(3 DOWNTO 0); LED:OUT STD_LOGIC_VECTOR(6 DOWNTO 0);END COMPONENT ;COMPONENT MULXPORT(CLK:IN STD_LOGIC; CLR:IN STD_LOGIC; EN:IN STD_LOGIC; S_1MS: IN STD_LOGIC_VECTOR(3 DOWNTO 0); S_10MS: IN STD_LOGIC_VECTOR(3 DOWNTO 0); S_100MS: IN STD_LOGIC_VECTOR(3 DOWNTO 0); S_1S: IN STD_LOGIC_VECTOR(3 DOWNTO 0); S_10S: IN STD_LOGIC_VECTOR(3 DOWNTO 0); M_1MIN: IN STD_LOGIC_VECTOR(3 DOWNTO 0); M_10MIN: IN STD_LOGIC_VECTOR(3 DOWNTO 0); HOUR: