1、 AQUILACPUChip Set Remarks:P4-BANIAS:MCH-M ODEM:TEMPModel Name PBA Name PCB Code Dev. StepRevision:AQUILA MAIN BA92-01774A BA41-#A SR1.0DRAWCHECKAPPROVAL7 Schematic Diagrams and PCB Silkscreen7-1 MAIN BOARD7-1-1 Schematic DiagramsX107-17 Schematic Diagrams and PCB Silkscreen7-1-1(a) Main Board Schem

2、atic Sheet 2 of 39(Operation Block Diagram)7-2X10PSB 400MHZ TFT_LCD 14.1EXTERNALMCH-M200 / 266 MHZCRTGRAPHICAGP 4X , 1.5VDOUBLE DATA RATEODEM 1.2 Vnvidia MAP31593 FCBGAUSB 0 , 12 USBHUB I / FBLUETOOTH1.8V 8BIT 66MHZRJ -11 MDCFINGER PRINTINNER SPEAKER AUDIO CODECICH4 - MHEAD PHONECIRRUS LOGIC SAC97 L

3、INK82801 DBM 1.5V cs4202IDE 0421 FCBGAEXTERNAL MICIDE 1LOW PIN COUNTAC97 LINKFWHHDDIDE 0SLIMMICOMDVD-CD/RWIDE 1HITACHI SCOMBOHD64F2169LOMKEYBOARD3 COM STOUCHPAD3C920 - ST05PCI BUSMEMORY STICKport replicatorPCI BUSCARDBUS CONTROLLERMINI PCI RICOH R5C590CARDBUSWLAN WLAN &1394 BLUETOOTHCOMBOU B 2USB 3P

4、ORT REPLICATORSUPER I/O PC87393SERIAL I/O PARALLEL I/ORJ -45SPDIFTV (S-VHS)PS /2USB 4,5DC - INSYSTEM MEMORY2 EA SODIMMMAX 512MBYTE EACHCPU 479 MICRO FCBGA7 Schematic Diagrams and PCB Silkscreen7-1-1(b) Main Board Schematic Sheet 3 of 39(Board Information)X107-3SCHEMATIC ANNOTATIONS AND BOARD INFORMA

5、TIONPCI DevicesVoltage RailsDevicesIDSEL#REQ/GNT#InterruptsCardbusAD190A,B,CVDCPrimary DC system power supply (7 to 21V)LANAD213DVCC_CORECore voltage for BANIAS CPU (1.356 - 0.844V)MiniPCI SLOT1AD232E,FVCCPBANIAS/ODEM Processor System Bus(PSB) Termination (1.05V)USBAD29(internal)-USB2.0 #0 : AVCC_MC

6、HMCH-M Core Voltage (1.2V)USB2.0 #1 : DUSB2.0 #2 : CP1.5V1.5V switched power rail (off in S3-S5)Hub to PCIAD30(internal)-P1.5V_AUX1.5V power rail (off in S4-S5)LPC bridge/IDE/AC97/SMBUSAD31(internal)-BP1.8V1.8V switched power rail (off in S3-S5)AGPAD17(internal)-A,BP1.8V_AUX1.8V power rail(off in S4

7、-S5)Internal MACAD24(internal)-EP2.5V2.5V switched power rail (off in S3-S5)AC Link-BP2.5V_AUX2.5V power rail (off in S4-S5) P1.25V_AUX1.25V power rail (off in S4-S5) MICOM_P3V3.3V always on power rail for MICOM P3.3V3.3V switched power rail (off in S3-S5)DockingAD30(internal)-P3.3V_AUX3.3V power ra

8、il (off in S4-S5)PCI SLOTAD20-A,B,C,DP3.3V_ALWAYS 3.3V always on Power RailP5V5.0V switched power rail (off in S3-S5) P5V_ALWAYS 5.0V always on powerP12V12.0V switched power rail (off in S3-S5)CPU Core Voltage Table2VID5 VID4 VID3 VID2 VID1 VID0VoltageVID5 VID4 VID3 VID2 VID1 VID0VoltageI C / SMB Ad

9、dress0 0 0 0 0 0 01.708 V1 00 0 01.196 V Northwood-BDevicesAddressHexBus 0 0 0 0 0 11.692 V10 0 0 0 11.180 V (Interposer Bd)0 0 0 0 1 011.67660 V10 0 0 1 011.16448 VICH4Master-SMBUS MasterADM1032(CPU Thermal Sensor) 1001 110X9ChThermal Sensor0 0 0 1 0 01.644 V10 0 1 0 01.132 VSODIMM01010 0000A0h-0 0

10、 0 1 0 11.628 V10 0 1 0 11.116 VSODIMM11010 001XA2h-0 -0 0 1 1 01.612 V1 -0 0 1 1 01.100 VCK-408 (Clock Generator)1101 001xD2hClock, Unused Clock Output Disable- 0 0 1 1 11.596 V1 0 0 1 1 11.084 V0 0 1 0 0 01.580 V10 1 0 0 01.068 V0 0 1 0 0 11.564 V 1 1 00 0 11.052 V0 0 1 0 1 01.548 V10 1 0 1 01.036

11、 V0 0 1 0 1 11.532 V10 1 0 1 11.020 V0 0 1 1 0 01.516 V10 1 1 0 01.004 V0 0 1 1 0 11.500 V10 1 1 0 10.988 VUSB PORT Assign0 0 1 1 1 01.484 V10 1 1 1 00.972 V0 0 1 1 1 11.468 V10 1 1 1 10.956 V01 0 0 0 01.452 V11 0 0 0 00.940 VPORT NUMBERASSIGNED TO 01 0 0 0 11.436 V11 0 0 0 10.924 V01 0 0 1 01.420 V

12、11 0 0 1 00.908 V0SYSTEM PORT A01 0 0 1 11.404 V11 0 0 1 10.892 V1SYSTEM PORT B01 0 1 0 01.388 V11 0 1 0 00.876 V2BLUETOOTH01 0 1 0 101.372 V11 0 110.860 V3FINGER PRINTHighest Freq. 0 1 0 1 1 1 01.356 V101 1 00.844 V Lowest Freq.4PORT REPLICATOR-0 1 0 1 1 111.340 V1 1 0 1 1 10.828 V5PORT REPLICATOR0

13、1 1 0 0 01.324 V11 1 0 0 00.812 V01 1 0 0 11.308 V11 1 0 0 10.796 V01 1 0 1 01.292 V11 1 0 1 00.780 V01 1 0 1 11.276 V11 1 0 1 10.764 VSystem Power States01 1 1 0 01.260 V11 1 1 0 00.748 V Deeper Sleep01 1 1 0 11.244 V11 1 1 0 10.732 VCHP3_SLPS1* S1, Powered-On-Suspend(POS) : In this state, all cloc

14、ks(except the 32.768KHz clock) are stopped.01 1 1 1 011.228 V11 1 100.716 VThe system context is maintained in system DRAM. Power is maintained to PCI, the CPU, memory controller, memory, and all other criticial subsystems.01 1 1 1 11.212 V11 1 1 1 10.700 VNote that this state does not preclude powe

15、r being removed from non-essential devices, such as disk drives. During this state, CPU can be selectedfor either Deep Sleep or Deeper Sleep.In Deeper Sleep, CPU voltage reduced in this state to reduce the leakage power.CHP3_SLPS3* S3, Suspend-To-RAM(STR) : The system context is maintained in system

16、 DRAM, but power is shut off to non-critical circuits.Memory is retained, and refreshes continue. All clocks stop except RTC clock.CHP3_SLP4S* S4, Suspend-To-Disk(STD) : The Context of the system is maintained on the disk. All power is then shut off to the system except for the logic required to res

17、ume.Externally appears same as S5, but may have different wake events.CHP3_SLPS5* S5, Soft Off(SOFF) : System context is not maintained. All power is shut off except for the logic required to restart. A full boot is required when waking.REVISION HISTORYSee rev notes in the changes file for more info

18、rmation.7 Schematic Diagrams and PCB Silkscreen7-1-1(c) Main Board Schematic Sheet 4 of 39(Clock Generator)7-4X10CY28346optionICS950810No StuffCLK0_HCLK2* CLK0_HCLK2CLK0_ITP*CLK0_ITPNo Stuff OPTION682088NO STUFFP/N : 1209-001370NO STUFFSEL1 SEL0 HOST CLK 0066MHz01100MHz10200MHz11133MHz7 Schematic Di

19、agrams and PCB Silkscreen7-1-1(d) Main Board Schematic Sheet 5 of 39(Banias CPU)X107-57 Schematic Diagrams and PCB Silkscreen7-1-1(e) Main Board Schematic Sheet 6 of 39(Banias CPU)7-6X10CLK0_HCLK2 CLK0_HCLK2*Placed as close as possible to each of the four VCCA pins.VCCA, VCCQ CHECK ?CPU1_PREQ* CPU1_

20、PRDY* CPU1_BPM3* CPU1_BPM2*CPU1_BPM1* CPU1_BPM0*GTLREF : Keep the Voltage divider within 0.5of the First GTLREF0 with Z0= 55 ohm traceCPU1_TDOMinimize coupling of any switching signals to this netCOMP 0 , 2 SCK/SCK#0 = SCK/SCK#1 = SCK/SCK#2RCVEN Sinal must be routed on the same layer as the memory c

21、locks. SCK/SCK#3 = SCK/SCK#4 = SCK/SCK#5 Differential clock length must be 12 longer than Strobe signals. Differential clock length must be 13 longer than Control and Command signals.7 Schematic Diagrams and PCB Silkscreen7-1-1(i) Main Board Schematic Sheet 10 of 39(MCH-M)7-10X10NO STUFF40.2 ohm(Hea

22、therCanyon0.9)NO STUFF RSVD1, RSVD2, ETS CHECK ? Place near MCH Place near AGPNO STUFFST1 ST2 MCH Strap X1DDR0 XTEST1 X400 MHz7 Schematic Diagrams and PCB Silkscreen7-1-1(j) Main Board Schematic Sheet 11 of 39(DDR-SODIMM)X107-11P/N : 3709-001193P/N : 3709-0011967 Schematic Diagrams and PCB Silkscree

23、n7-1-1(k) Main Board Schematic Sheet 12 of 39(DDR-S Termination)7-12X107 Schematic Diagrams and PCB Silkscreen7-1-1(l) Main Board Schematic Sheet 13 of 39(DDR-P Termination)X107-13Place 1 Cap close to every 2 pullup resisters terminated to +V1.257 Schematic Diagrams and PCB Silkscreen7-1-1(m) Main Board Schematic Sheet 14 of 39(ICH-4)7-14X10NO STUFFPlace resi