1、一位全加器真值表一位全加器真值表一位全加器的邏輯表達(dá)式S=A B CinCo=AB+BCin+ACin其中A,B為要相加的數(shù)，Cin為進(jìn)位輸 入；S為和，Co是進(jìn)位輸出；Library ieee;Use ieee.std_logic_1164.all;Use ieee.std_logic_unsigned.all;Entity fulladder IsPort(Ci,a,b : IN std_logic; s,Co : OUT std_logic);End fulladder;Architecture m1 Of fulladder IsSignal tmp: std_logic_vector

2、(1 downto 0);Begin tmp=(0 & a) + b + Ci; s=tmp(0); Co=tmp(1);End m1;一位全加器的數(shù)據(jù)流（邏輯）描述Library ieee;Use ieee.std_logic_1164.all;Use ieee.std_logic_unsigned.all;Entity fulladder isPort (A,B,CI:in std_logic; S,CO:out std_logic);End fulladder;Architecture dataflow of fulladder isBeginS= CI xor A xor B;CO=

3、(A and B) or (CI and A) or (CI and B);End dataflow;一位全加器的行為描述Library ieee;Use ieee.std_logic_1164.all;Use ieee.std_logic_unsigned.all;Entity fulladder is Port (a,b,cin: In bit; sum,cout: Out bit);End fulladder;Architecture behave Of fulladder IsBegin Process (a, b, cin) Begin If(a Or b Or cin)= 0 Th

4、en sum =0; cout =0; Elsif (a AND b AND cin ) =1 Then sum =1; cout =1; Elsif (a XOR b XOR cin ) =0 Then sum =0; cout =1; Else sum =1; cout =0; End If; End Process;End behave;4位全加器的設(shè)計(jì)，先設(shè)計(jì)4個(gè)1位的全加器，然后將低位的進(jìn)位輸出與高位的進(jìn)位輸入相連，將要進(jìn)行加法運(yùn)算的兩個(gè)4位數(shù)的每一位分別作為每一個(gè)1位全加器的輸入，進(jìn)行加法運(yùn)算，所有的1位全加器的輸出組成一個(gè)4位數(shù)，即輸入的兩個(gè)4位數(shù)之和，最高位的全加器產(chǎn)生的進(jìn)位輸

5、出即兩個(gè)4位數(shù)求和的進(jìn)位輸出。（如圖）Library ieee;Use ieee.std_logic_1164.all;Use ieee.std_logic_unsigned.all;Entity adder4 IsPort(Cin : IN std_logic; x, y : IN std_logic_vector(3 downto 0); sum : OUT std_logic_vector(3 downto 0); Cout : OUT std_logic);End adder4;Architecture ax Of adder4 Is Signal c: std_logic_vecto

6、r(0 to 4); Component fulladder Port(Ci,a,b : IN std_logic; s, Co : OUT std_logic); End component;Begin c(0)c(0),a=x(0),b=y(0), s=sum(0),Co=c(1); U 2 : f u l l a d d e r P o r t Map(c(1),x(1),y(1),sum(1),c(2); U 3 : f u l l a d d e r P o r t Map(c(2),x(2),y(2),sum(2),c(3); U 4 : f u l l a d d e r P o

7、 r t Map(c(3),x(3),y(3),sum(3),c(4); Cout=c(4);End ax;library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity adder4bit is port(cin: in std_logic; a,b: in std_logic_vector(3 downto 0); s: out std_logic_vector(3 downto 0); cout: out std_logic );end adder4bit;architecture beh of adder4bit is signal sint: std_logic_vector(4 downto 0); signal aa,bb: std_logic_vector(4 downto 0);begin aa=