1、Spatial Discrete Model for Clustered Defects on Wafer Maps空間統(tǒng)計(jì)模型在半導(dǎo)體制造質(zhì)量研究中的應(yīng)用Personal profile and Lab introduction王好：博士研究生，2010-2014年就讀于天津大學(xué)工業(yè)工程系，2014年至今就讀于清華 大學(xué)工業(yè)工程系。導(dǎo)師：王凱波，博士，博士生導(dǎo)師，2006年在香港科技大學(xué)獲得博士學(xué)位（工業(yè)工程與 工程管理學(xué)），2007年加入清華大學(xué)工業(yè)工程系，現(xiàn)為教授。王凱波博士的主要研究方 向?yàn)榻y(tǒng)計(jì)質(zhì)量控制以及數(shù)據(jù)分析，并強(qiáng)調(diào)融合工程知識與統(tǒng)計(jì)方法解決工業(yè)實(shí)際質(zhì)量問 題。Some rese

2、arch topics in our Lab:Robust Parameter Design For Profile ControlProfile Monitoring And DiagnosticsSpatial And Temporal Models For Carbon Nanotube Height Variations 3D Print Quality Control: Distortion And ShrinkageSpatial Correlated Defects Model On Wafer Maps (Todays Topic)Introduction of ICs & c

3、hipsIntegrated Circuits (ICs):One of the most wildly used electronic components in industrial production and daily life.Chips:A realization of ICChips are a set of electronic circuits electricallyinterconnected on semiconductor material plates (wafers) to fulfilcomplex electric functions.Used as ele

4、ctric components (CPU,RAM)Relationship between Semiconductor wafer and IC chipsWafer : Plane piece made by semiconductor materialsChips:Integrated circles“planted on waferwaferchipFigure1.Real wafersFigure 2. Relationship between Semiconductorwafer (left) and IC chip (right)Figure3. Flow diagram for

5、 generic IC process sequenceYield study: Vital indicators in semiconductor fieldsHigh production input:Billions of dollars to build a factoryOver two hundred process steps ,half a month.Unsatisfactory output:(Above 10% or even all) chips could be unqualified.Quite a lot of materials, time and resour

6、ces wastedYield analysis to:Predict the future outcomes.Monitor the processFind the root cause of defectives.Improve revenues of enterprise.5Yield study: Vital indicators in semiconductor fieldsYield: fraction of output and input，usually 3090% on a wafer.According to the sequential yield loss proces

7、ses：Wafer process yield Y,: percentage of wafers arriving at probing step;Wafer probe yield Y : percentage that getting through the testing step;Assembly yield Y caused by the assembly process;Final test yield Y : percentage that make through the final electrical test.Yield loss from wafer probe (Y)

8、 is the highest in chips manufacturing processes.Real Examples of Wafer probe yield(Program with Samsung Electronics Co., Ltd. )Wafer probe yield Y: percentage that getting through the testing step;Traditional SPC tools: c chart or p chartIgnore chip level yields and only focus on total yields throu

9、gh a waferCollect yields wafer by wafer.(2)Build control limits(3)Monitoring the process: abnormal alarms.Advantages：Easy for applicationProvide some basic information about wafer yieldsDisadvantages:Loss of informationFocus on chip yield and sum up to wafer yield : identical defects rate distributi

10、ons for each location1) Poisson model , identical defects rate at each location Probability that any specific chip containing x defects:2) Negative binomial (NB) model3) Lambert (1992) described zero-inflated Poisson (ZIP) regression 1Assumption:There is a random shock leading to Poisson /binomial/

11、NB processes andThis random shock occurs independently with probability p.1 Zero-inflated Poisson regression, with an application to defects in manufacturing, Technometrics, Taylor & Francis, 1992, 34, 1-14(1) Take chips as independent and identical samples(2) If the wafer presents significant spati

12、al patterns:(3) Not really consider each chip locations defects rate; Just assume identical distribution for each chip.Short comes of the previous modelsIndependent assumptions of traditional statistics violates real production features !In the view of spatial statistics:Characteristics at proximal

13、locations appear to be correlated, either positively or negatively.Literatures Review :How to capture spatial pattern?Answer of Bae et al. (2007) 1 : By spatial coordinate.GLSp model:a function of the chips polar coordinates.Successfully captured the global trend of defect rates but failed to captur

14、e the local clustering:Real defects mapRegressed defects rate1Bae, S. J.; Hwang, J. Y. & Kuo, W. Yield prediction via spatial modeling of clustered defect counts across a wafer map IIE Transactions, Taylor & Francis,2007, 39, 1073-1083Proposed modelVision of geographical statistics:Spatial coordinat

15、es - Capture macro scale tendencySpatial random error Capture micro scale correlation of the densitys distribution across a wafer map.STAGE 1: Poisson distribution modelAt the stage 1, we assume the number of defects of the chip on the location has independent Poisson distribution given density .(1)

16、 On each location ,(2) Each chip has its own defects rate , determined by its location and neighbors;(3) A Poisson process determines the real defects showed on this location.(4) For total sites on a wafer map, there are different Poisson process:The expected value of the observed data is linear rel

17、ated to some predictivevariables via inverse link function:a function of the chips polar coordinatesSTAGE 2: Generalized linear function: predictive variables for the Poisson parameterSTAGE 2B: Assignment of Auto-correlationsFigure 7. Neighbors structure of instrinsic GMRF on wafer map,blue lattices

18、 are designated as neighborsFull conditions parameterization:Models implementation on real datasetFigure 7. Real wafer map and typical simulated wafer map showing defects pattern and numbers in each chipFigure 8(a) linear fitted predictors posterior mean of spatial correlation component total fittedTable 1. Moran I statistic under randomization for residuals in two modelsModels implementation on real datasetDATA-2 :Defects are randomly scattered onwafer map.DATA-3:Present some ringlike patternsDATA-4:bottom-right clustered on wafer map.Table 2. DIC values for GLSp-iCAR and GLSp mod