先進芯片封裝知識介紹第一頁，共34頁。OutlinePackageDevelopmentTrend3DPackageWLCSP&FlipChipPackage2020/11/302第二頁，共34頁。PackageDevelopmentTrend2020/11/303第三頁，共34頁。SOFamilyQFPFamilyBGAFamilyPackageDevelopmentTrend2020/11/304第四頁，共34頁。CSPFamilyMemoryCardSiPModulePackageDevelopmentTrend2020/11/305第五頁，共34頁。3DPackage3DPackage2020/11/306第六頁，共34頁。3DPackageIntroductionetCSPStackFunctionalIntegrationHighLowTape-SCSP(orLGA)S-CSP(orLGA)S-PBGAS-M2CSPStacked-SiP2ChipStackWirebond2ChipStackFlipChip&WirebondMultiChipStackPackageonPackage(PoP)StackingSS-SCSP(film)FS-BGA3S-PBGAS-SBGAS-TSOP/S-QFP

3S-CSPS-etCSPetCSP+S-CSP

PS-fcCSP+SCSP

PoPwithinterposerFS-CSP2FS-CSP1PaperThinPS-vfBGA+SCSPPiP

5SCSPSS-SCSP(paste)UltrathinStackD2D3D4D2D2D3D4D2

PoPQFN4SS-SCSP2020/11/307第七頁，共34頁。StackedDieTopdieBottomdieFOWmaterilWire2020/11/308第八頁，共34頁。TSVTSV(ThroughSiliconVia) Athrough-siliconvia(TSV)isaverticalelectricalconnection(via)passingcompletelythroughasiliconwaferordie.TSVtechnologyisimportantincreating3Dpackagesand3Dintegratedcircuits.

A3Dpackage(SysteminPackage,ChipStackMCM,etc.)containstwoormorechips(integratedcircuits)stackedverticallysothattheyoccupylessspace. Inmost3Dpackages,thestackedchipsarewiredtogetheralongtheiredges.Thisedgewiringslightlyincreasesthelengthandwidthofthepackageandusuallyrequiresanextra“interposer”layerbetweenthechips. Insomenew3Dpackages,through-siliconviareplaceedgewiringbycreatingverticalconnectionsthroughthebodyofthechips.Theresultingpackagehasnoaddedlengthorthickness.WireBondingStackedDieTSV2020/11/309第九頁，共34頁。What’sPoP?PoPisPackageonPackageTopandbottompackagesaretestedseparatelybydevicemanufacturerorsubcon.

PoP2020/11/3010第十頁，共34頁。PoPPS-vfBGAPS-etCSPLowLoopWirePinGateMoldPackageStackingWaferThinningPoPCoreTechnology2020/11/3011第十一頁，共34頁。PoPAllowsforwarpagereductionbyutilizingfully-moldedstructureMorecompatiblewithsubstratethicknessreductionProvidesfinepitchtoppackageinterfacewiththrumoldviaImprovedboardlevelreliabilityLargerdiesize/packagesizeratioCompatiblewithflipchip,wirebond,orstackeddieconfigurationsCosteffectivecomparedtoalternativenextgenerationsolutionsAmkor’sTMV?PoPTopviewBottomviewThroughMoldVia2020/11/3012第十二頁，共34頁。PoP

BallPlacementontopsurfaceBallPlacementonbottomDieBondMold(UnderFulloptional)LaserdrillingSingulationFinalVisualInspectionBaseM’tlThermaleffectProcessFlowofTMVPoP2020/11/3013第十三頁，共34頁。Digital(Btmdie)+Analog(Middledie)+Memory(Toppkg)PotableDigitalGadgetCellularPhone,DigitalStillCamera,PotableGameUnitMemorydieAnalogdieDigitaldiespacerEpoxyPiP2020/11/3014第十四頁，共34頁。EasysystemintegrationFlexiblememoryconfiguration100%memoryKGDThinnerpackagethanPOPHighIOinterconnectionthanPOPSmallfootprintinCSPformatIthasstandardballsizeandpitchConstructedwith:FilmAdhesivedieattachEpoxypasteforTopPKGAuwirebondingforinterconnectionMoldencapsulationWhyPiP?

PiP2020/11/3015第十五頁，共34頁。MaterialforHighReliabilityBasedonLowWarpageWaferThinningFineProcessControlTopPackageAttachDieAttachetcOptimizedPackageDesignFlipChipUnder-fillTopepoxyISMPiPCoreTechnology

PiP2020/11/3016第十六頁，共34頁。MemoryPKGSubstrateFlipchipMemoryPKGFlipchipInnerPKGAnalogAnalogSpacerDigitalInnerPKGWBPIPFCPIPPiPPiP–W/BPiPandFCPiP

2020/11/3017第十七頁，共34頁。WLCSP&FlipChipPackage2020/11/3018第十八頁，共34頁。WLCSPWhatisWLCSP? WLCSP(WaferLevelChipScalePackaging),isnotsameastraditionalpackagingmethod(dicingpackagingtesting,packagesizeisatleast20%increasedcomparedtodiesize). WLCSPispackagingandtestingonwaferbase,anddicinglater.Sothepackagesizeisexactlysameasbarediesize.

WLCSPcanmakeultrasmallpackagesize,andhighelectricalperformancebecauseoftheshortinterconnection.2020/11/3019第十九頁，共34頁。WLCSPWhyWLCSP?Smallestpackagesize:WLCSPhavethesmallestpackagesizeagainstdiesize.Soithaswidelyuseinmobiledevices.Highelectricalperformance:becauseoftheshortandthicktraceroutinginRDL,itgiveshighSIandreducedIRdrop.Highthermalperformance:sincethereisnoplasticorceramicmoldingcap,heatfromdiecaneasilyspreadout.Lowcost:noneedsubstrate,onlyonetimetesting.WLCSP’sdisadvantageBecauseofthediesizeandpinpitchlimitation,IOquantityislimited(usuallylessthan50pins).BecauseoftheRDL,staggerIOisnotallowedforWLCSP.2020/11/3020第二十頁，共34頁。RDLRDL:RedistributionLayerAredistributionlayer(RDL)isasetoftracesbuiltuponawafer’sactivesurfacetore-routethebondpads.

Thisisdonetoincreasethespacingbetweeneachinterconnection(bump).2020/11/3021第二十一頁，共34頁。WLCSPProcessFlowofWLCSP2020/11/3022第二十二頁，共34頁。WLCSPProcessFlowofWLCSP2020/11/3023第二十三頁，共34頁。FlipChipPackageFCBGA(PassiveIntegratedFlipChipBGA)(PI)-EHS-FCBGA(PassiveIntegratedExposedHeatSinkFlipChipBGA)(PI)-EHS2-FCBGA(PassiveIntegratedExposed2piecesofHeatSinkFlipChipBGA)MCM-FCBGA(Multi-Chip-ModuleFCBGA)PI-EHS-MP-FCBGA(PassiveIntegratedExposedHeatSinkMultiPackageFlipChip)2020/11/3024第二十四頁，共34頁。Bump2020/11/3025第二十五頁，共34頁。BumpDevelopment2020/11/3026第二十六頁，共34頁。BumpDevelopment2020/11/3027第二十七頁，共34頁。BumpDevelopment2020/11/3028第二十八頁，共34頁。C4FlipChipWhat’sC4FlipChip?C4is:ControlledCollapsedChipConnectionChipisconnectedtosubstratebyRDLandBumpBumpmaterialtype:solder,gold2020/11/3029第二十九頁，共34頁。C4FlipChipBGAMainFeaturesBallPitch:0.4mm-1.27mmPackagesize:upto55mmx55mmSubstratelayer:4-16LayersBallCount:upto2912

TargetMarket:

CPU、FP