QuicklogicArcticLink可編程連接平臺(tái)設(shè)計(jì)QuicklogicArcticLink可編程連接平臺(tái)設(shè)計(jì)方案ArcticLink可編程連接解決方案平臺(tái)采用0.18um六層金屬CMOS工藝制造,內(nèi)核電壓為1.8V,I/O電壓可設(shè)定為1.8V,2.5V和3.3V.ArcticLink的邏輯單元為640個(gè),集成了高速USB2.0OTG控制器,SD/SDIO/MMC/CE-ATA主控制器,ASSP/FPGA接口,以及靈活的可編程架構(gòu),可編程I/O,非常低功耗模式和安全鏈接.本文介紹了ArcticLink主要特性,解決方案平臺(tái)方框圖,連接解決方案方框圖,以及各種USBOTG連接框圖，在汽車內(nèi)裝藍(lán)牙免提，智能手機(jī)，PND/PMP和ePOS的應(yīng)用框圖．

TheQuickLogicArcticLinkSolutionPlatformisfabricatedona0.18μm,sixlayermetalCMOSprocess.Thecorevoltageis1.8V.TheI/Ovoltageinputtoleranceandoutputdrivecanbesetas1.8V,2.5V,and3.3V.

ArcticLink器件亮點(diǎn):

Hi-SpeedUSB2.0OTGController

?SingleportOTGwithembeddedhigh-speedPHY

?Optional12-signalULPIinterface

?Full-speedCEA-936-Amini-USBanalogcarkitinterface

?DedicatedDMAcontroller

?High-speedupto480Mbits/sec.

SD/SDIO/MMC/CE-ATAHostController

?SD/SDIO1-bitor4-bitupto52MHzwithSecureDigitalHighCapacity(SDHC)support

?CE-ATA1-bit,4-bitor8-bitupto52MHz

?MMC1-bit,4-bitor8-bitupto52MHz

?High-speedandflexibletosupportmultiplestorageoptionsandSDIOperipherals

ASSP/FPGAInterface

?8Kbytesscratchpadmemory

?FlexibleHostinterfaceforUSBandSD/SDIO/MMC/CE-ATAports

?DMAandpowermanagementfunctions

?Directmemoryapertureforperipheralsubsystems

FlexibleProgrammableFabric

?0.18μm,sixlayermetalCMOSprocess

?1.8Vcorevoltage,1.8/2.5/3.3VdrivecapableI/Os

?36KbitsofSRAM–sevendual-port4-KbithighperformanceSRAMblocks

?Embeddedsynchronous/asynchronousFIFOcontrollers

?Oneuserconfigurableclockmanager(CCM)(110-ballWLCSPand196-ballTFBGApackagesonly)

?Upto120programmableI/Osavailable

?100,000systemgates

?Nonvolatile,instant-on

?IEEE1149.1boundaryscantestingcompliant

ProgrammableI/O

?Bankprogrammabledrivestrength

?Bankprogrammableslewratecontrol

?IndependentI/ObankscapableofsupportingmultipleI/Ostandardsinonedevice

?NativesupportforDDRIOs(196-ballpackageonly)

?BankprogrammableI/Ostandards:LVTTL,LVCMOS,andLVCMOS18

?CanbeusedforlevelshifterandI/Ovoltagetranslator

VeryLowPower(VLP)Mode

?TheQuickLogicArcticLinkSolutionPlatformhasaspecialVLPpinwhichcanenablealowpowersleepmodethatsignificantlyreducestheoverallpowerconsumptionofthedevicebyplacingthedeviceinstandby.

?Enter/exitVLPmodefrom/tonormaloperationinlessthan250μs(typical)

SecurityLinks

ThereareseveralsecuritylinkstodisableJTAGaccesstothedevice.ProgrammingtheseoptionallinkscompletelydisablesaccesstothedevicefromtheoutsideworldandprovidesanextralevelofdesignsecuritynotpossibleinSRAM-basedFPGAs.

JTAG

QuickLogicArcticLinkSolutionPlatformsupportsIEEE1149.1boundaryscanorpost-manufacturingtestability.Externalaccesstothisfeaturecanbecompletelydisabled.

ArcticLinkQL1A100主要特性列表:

圖1.ArcticLink解決方案平臺(tái)方框圖

圖2.ArcticLink連接解決方案方框圖

圖3.QL1A100和USB1.1與OTG的連接框圖

圖4.QL1A100和ULPIHSPHY/USB1.1串行收