.2頂層模塊該模塊主要實現(xiàn)將各個模塊綜合組成多功能電子萬年歷系統(tǒng)，其包括：主控制模塊，秒表模塊，時間及其設(shè)置模塊，鬧鐘模塊，時間顯示動態(tài)位選模塊及顯示模塊，分頻模塊，該頂層模塊結(jié)果功能如圖22所示。圖22頂層模塊結(jié)構(gòu)功能圖第三章系統(tǒng)仿真與調(diào)試3.1主控制模塊（maincontrol）圖23主控制模塊的波形仿真圖3.2時間及其設(shè)置模塊（time_auto_and_set）①時間模塊（timepiece_main）圖24時間模塊的波形仿真圖②時間設(shè)置模塊（timeset）圖25時間設(shè)置模塊的波形仿真圖③時間數(shù)據(jù)與時間設(shè)置數(shù)據(jù)多路選擇模塊（time_mux）圖26多路選擇模塊的波形仿真圖3.3時間顯示動態(tài)位選模塊（time_disp_select）圖27時間顯示動態(tài)位選模塊的波形仿真圖圖28時間顯示動態(tài)位選模塊的波形仿真圖3.4顯示模塊（disp_data_mux）圖29顯示模塊的波形仿真圖3.5秒表模塊（stopwatch）圖30秒表功能的波形仿真圖3.6鬧鐘模塊（alarmclock）圖31鬧鐘模塊的波形仿真圖3.7分頻模塊（fdiv）圖32分頻模塊的波形仿真圖總結(jié)這次的課題是基于FPGA的多功能電子萬年歷的設(shè)計，完成此次設(shè)計的過程中，從最開始對FPGA以及電子萬年歷原理的不了解，到后來導(dǎo)師提供的資料、與同學(xué)的交流討論，再到獨自設(shè)計整體的系統(tǒng)、實物的制作，在這個過程中有很多收獲。通過這次課題，我基本了解和掌握了FPGA的基本操作，深入學(xué)習(xí)了VHDL語言與VerilogHDL語言等多種計算機語言，了解了電子萬年歷這類電子時鐘的工作運行原理。在編輯程序代碼的過程中，會出現(xiàn)很多編輯錯誤和語句的邏輯不順，在作品實物的焊接燒錄過程中，也出現(xiàn)了接觸不良以及電子元件損壞的問題，不過這些問題都基本解決。運用FPGA技術(shù)可無限地重新編程，加載一個新的設(shè)計方案不到一秒鐘，可以減少大量的硬件開銷。但是也存在明顯的缺點，就是FPGA的所有功能都只能依靠硬件實現(xiàn)，無法實現(xiàn)分支條件跳轉(zhuǎn)等操作，設(shè)計的靈活度與通用處理器相比有很大的差距。此次畢業(yè)設(shè)計，在作品的完成過程中遇到了很多問題，在尋找解決辦法時，自己也學(xué)到了很多，也更加拓寬了自己的眼界和認(rèn)識，當(dāng)然也發(fā)現(xiàn)自己所存在的很多不足，例如對VHDL計算機語言的理解不足、對QuartusII軟件應(yīng)用的不熟練、對整個系統(tǒng)的整體把握的能力還不夠、程序的編寫和調(diào)試能力有待進一步加強等。經(jīng)過此次設(shè)計之后，堅定了自己在今后的生活和工作中加強對理論及實際應(yīng)用的學(xué)習(xí)，懂得了不斷學(xué)習(xí)的重要性。參考文獻[1]帕爾尼卡、夏宇聞.VERILOGHDL數(shù)字設(shè)計與綜合,電子工業(yè)出版社，2004.[2]褚振勇，翁木云.FPGA設(shè)計與應(yīng)用（第二版），西安電子科技大學(xué)出版社，2006.[3]侯伯亨，顧新.VHDL硬件描述語言與數(shù)字邏輯電路設(shè)計修訂版，西安電子科技大學(xué)出版社，2004.[4]趙曙光，郭萬有.可編程邏輯器件原理，西安電子科技大學(xué)出版社，2000.[5]徐志軍，徐光輝.CPLD/FPGA的開發(fā)與應(yīng)用，電子工業(yè)出版社，2002.[6]冼進，戴仙金，潘懿萱.VerilogHDL數(shù)字控制系統(tǒng)設(shè)計實例，中國水利水電出版社，2007.[7]夏宇聞.VerilogHDL數(shù)字系統(tǒng)設(shè)計教程，北京航空航天大學(xué)出版社，2003.[8]黃智偉.FPGA系統(tǒng)設(shè)計與實踐,電子工業(yè)出版社，2003.[9]王金明等.數(shù)字系統(tǒng)設(shè)計與verilogHDL,電子工業(yè)出版社，2002.附錄多功能電子萬年歷系統(tǒng)的VerilogHDL語言程序設(shè)計部分代碼1modulekey_res( input clk , input rst , input key1_sig , input key2_sig , input key3_sig , input key4_sig , output reg [3:0] set_num , output reg [2:0] set_hms_num , output key2_rise , output key3_rise , output key4_rise );reg key1_sig_r0;reg key1_sig_r1;reg key2_sig_r0;reg key2_sig_r1;reg key3_sig_r0;reg key3_sig_r1;reg key4_sig_r0;reg key4_sig_r1;assign key2_rise=key2_sig_r0&(~key2_sig_r1);assign key3_rise=key3_sig_r0&(~key3_sig_r1);assign key4_rise=key4_sig_r0&(~key4_sig_r1);always@(posedgeclkornegedgerst)begin if(!rst) begin key1_sig_r0<=1'b0; key1_sig_r1<=1'b0; end else begin key1_sig_r0<=key1_sig; key1_sig_r1<=key1_sig_r0; endendalways@(posedgeclkornegedgerst)begin if(!rst) begin key2_sig_r0<=1'b0; key2_sig_r1<=1'b0; end else begin key2_sig_r0<=key2_sig; key2_sig_r1<=key2_sig_r0; endendalways@(posedgeclkornegedgerst)begin if(!rst) begin key3_sig_r0<=1'b0; key3_sig_r1<=1'b0; end else begin key3_sig_r0<=key3_sig; key3_sig_r1<=key3_sig_r0; endendalways@(posedgeclkornegedgerst)begin if(!rst) begin key4_sig_r0<=1'b0; key4_sig_r1<=1'b0; end else begin key4_sig_r0<=key4_sig; key4_sig_r1<=key4_sig_r0; endendalways@(posedgeclkornegedgerst)begin if(!rst) set_num<=4'd0; elseif(key1_sig_r0&(~key1_sig_r1)) begin if(set_num==3) set_num<=4'd0; else set_num<=set_num+1'b1; endendalways@(posedgeclkornegedgerst)begin if(!rst) set_hms_num<=2'd0; elseif(set_num==2&&set_num==3) if(key2_rise) begin if(set_hms_num==1) set_hms_num<=2'd0; else set_hms_num<=set_hms_num+1'b1; endendEndmodule2moduleLCD_core( input clk, input rst, input Com_en, input [7:0] Com, input Data_en, input [7:0] Data, output reg lcd_rs, output wire lcd_rw, output reg [7:0] lcd_data, output reg lcd_en, output reg status );localparam IDLE =0;localparam LCD_COM =1;localparam LCD_DATA =2;localparam LCD_EN =3;localparam OVER =4;reg [3:0] cs;reg [3:0] ns;reg [7:0] state_cnt;assign lcd_rw=1'b0;always@(posedgeclkornegedgerst)begin if(!rst) cs<=IDLE; else cs<=ns;endalways@(*)begin ns=IDLE; case(cs) IDLE: begin if(Com_en==1'b1) ns=LCD_COM; elseif(Data_en==1'b1) ns=LCD_DATA; else ns=IDLE; end LCD_COM: begin if(state_cnt==8'd100) ns=LCD_EN; else ns=LCD_COM; end LCD_DATA: begin if(state_cnt==8'd100) ns=LCD_EN; else ns=LCD_DATA; end LCD_EN: begin if(state_cnt==8'd100) ns=OVER; else ns=LCD_EN; end OVER: begin ns=IDLE; end endcaseendalways@(posedgeclkornegedgerst)begin if(!rst) lcd_rs<=1'b1; elsecase(cs) LCD_COM: begin lcd_rs<=1'b0; end LCD_DATA: begin lcd_rs<=1'b1; end endcaseendalways@(posedgeclkornegedgerst)begin if(!rst) lcd_data<=8'd0; elsecase(cs) LCD_COM: begin lcd_data<=Com; end LCD_DATA: begin lcd_data<=Data; end endcaseendalways@(posedgeclkornegedgerst)begin if(!rst) lcd_en<=1'b0; elsecase(cs) LCD_EN: begin lcd_en<=1'b1; end default: begin lcd_en<=1'b0; end endcaseendalways@(posedgeclkornegedgerst)begin if(!rst) status<=1'b1; elseif(cs==OVER) begin status<=1'b1; end elseif(cs==IDLE&&ns!=IDLE) begin status<=1'b0; endendalways@(posedgeclkornegedgerst)begin if(!rst) state_cnt<=8'd0; elseif(cs==ns) state_cnt<=state_cnt+1'b1; else state_cnt<=8'd0;endEndmodule3modulestop_watch( input clk, input rst, input [3:0] set_num, input set_start, input set_stop, input set_clr, output reg [7:0] s0, //s0.s1s2 output reg [7:0] s1);localparam IDLE =4'd0;localparam CHECK =4'd1;localparam START =4'd2;localparam STOP =4'd3;localparam CLR =4'd4;reg [13:0] state_cnt;reg [3:0] cs;reg [3:0] ns;always@(posedgeclkornegedgerst)begin if(!rst) cs<=IDLE; else cs<=ns;endalways@(*)begin ns=IDLE; case(cs) IDLE: begin if(set_num==4'd1) ns=CHECK; else ns=IDLE; end CHECK: begin if(set_start==1'b1) ns=START; elseif(set_stop==1'b1) ns=STOP; elseif(set_clr==1'b1) ns=CLR; else ns=CHECK; end START: begin if(set_stop==1'b1) ns=STOP; else ns=START; end STOP: begin if(set_start==1'b1) ns=START; elseif(set_clr==1'b1) ns=CLR; else ns=STOP; end CLR: begin ns=CHECK; end endcaseendalways@(posedgeclkornegedgerst)begin if(!rst) s1<=8'd0; elsecase(cs) START: begin if(state_cnt==14'd10000) if(s1==8'd99) s1<=8'd0; else s1<=s1+1'b1; end CLR: begin s1<=8'd0; end endcaseendalways@(posedgeclkornegedgerst)begin if(!rst) s0<=8'd0; else begin if(s1==8'd99) if(s0==8'd99) s0<=8'd0; else s0<=s0+8'd1; endendalways@(posedgeclkornegedgerst)begin if(!rst) state_cnt<=14'd0; elseif(cs==ns) begin if(state_cnt==14'd1_000_0) state_cnt<=14'd0; else state_cnt<=state_cnt+1'b1; end else state_cnt<=14'd0;endEndmodule4moduletime_clock( input clk, input rst, input [3:0] set_num, input [1:0] set_hms_num, input set_up, input set_down, output reg [7:0] hours, output reg [7:0] minutes, output reg [7:0] seconds, output reg [7:0] alarm_hours, output reg [7:0] alarm_minutes, output reg alarm_en);reg [19:0] count;always@(posedgeclkornegedgerst)begin if(!rst) count<=20'd0; elseif(count==20'd1_000_000) count<=20'd0; else count<=count+1'b1;endalways@(posedgeclkornegedgerst)begin if(!rst) seconds<=8'd0; elseif(count==20'd1_000_000) begin if(seconds==8'd59) seconds<=8'd0; endendalways@(posedgeclkornegedgerst)begin if(!rst) minutes<=8'd0; elseif(seconds==8'd59) begin if(minutes==8'd59) minutes<=8'd0; else minutes<=minutes+1'b1; end elseif(set_num==4'd2) begin if(set_hms_num==2'd0) begin if(set_up==1'b1) begin if(minutes==8'd59) minutes<=8'd0; else minutes<=minutes+1'b1; end elseif(set_down==1'b1) begin if(minutes==8'd00) minutes<=8'd59; else minutes<=minutes-1'b1; end end endendalways@(posedgeclkornegedgerst)begin if(!rst) hours<=8'd0; elseif(minutes==8'd59) begin if(hours==8'd23) hours<=8'd0; else hours<=hours+1'b1; end elseif(set_num==4'd2) begin if(set_hms_num==2'd1) begin if(set_up==1'b1) begin if(hours==8'd23) hours<=8'd0; else hours<=hours+1'b1; end elseif(set_down==1'b1) begin if(hours==8'd00) hours<=8'd23; else hours<=hours-1'b1; end end endendalways@(posedgeclkornegedgerst)begin if(!rst) alarm_minutes<=8'd30; elseif(set_num==4'd3) begin if(set_hms_num==2'd0) begin if(set_up==1'b1) begin if(alarm_minutes==8'd59) alarm_minutes<=8'd0; else alarm_minutes<=alarm_minutes+1'b1; end elseif(set_down==1'b1) begin if(alarm_minutes==8'd00) alarm_minutes<=8'd59; else alarm_minutes<=alarm_minutes-1'b1; end end endendalways@(posedgeclkornegedgerst)begin if(!rst) alarm_hours<=8'd01; elseif(set_num==4'd3) begin if(set_hms_num==2'd0) begin if(set_up==1'b1) begin if(alarm_hours==8'd23) alarm_hours<=8'd0; else alarm_hours<=alarm_hours+1'b1; end elseif(set_down==1'b1) begin if(alarm_hours==8'd00) alarm_hours<=8'd23; else alarm_hours<=alarm_hours-1'b1; end end endendalways@(posedgeclkornegedgerst)begin if(!rst) begin alarm_en<=1'b0; end elseif(alarm_hours==hours&&alarm_minutes==minutes) alarm_en<=1'b1; else alarm_en<=1'b0;endEndmodule5moduletime_top( input clk , input rst , input [3:0] set_num , input [1:0] set_hms_num , input set_start , input set_stop_up , input set_clr_down , output reg [3:0] h1 , output reg [3:0] h2 , output reg [3:0] m1 , output reg [3:0] m2 , output reg [3:0] s1 , output reg [3:0] s2 , output alarm_en ); wire [7:0] ss0 ; //s0.s1s2wire [7:0] ss1 ;wire [7:0] hours ;wire [7:0] minutes ;wire [7:0] seconds ;wire [7:0] alarm_hours ;wire [7:0] alarm_minutes ;stop_watch U0( .clk ( clk ), .rst ( rst ), .set_num ( set_num ), .set_start ( set_start ), .set_stop ( set_stop_up ), .set_clr ( set_clr_down ), .s0 ( ss0 ), //s0.s1s2 .s1 ( ss1 ));time_clock U1( .clk ( clk ), .rst ( rst ), .set_num ( set_num ), .set_hms_num ( set_hms_num ), .set_up ( set_stop_up ), .set_down ( set_clr_down ), .hours ( hours ), .minutes ( minutes ), .seconds ( seconds ), .alarm_hours ( alarm_hours ), .alarm_minutes ( alarm_minutes ), .alarm_en ( alarm_en ));always@(posedgeclkornegedgerst)begin if(!rst) begin h1<=4'd0; h2<=4'd0; m1<=4'd0; m2<=4'd0;s1<=4'd0;s2<=4'd0; end elseif(set_num==1) begin h1<=4'd10; h2<=4'd10; m1<=ss0/8'd10; m2<=ss0%8'd10; s1<=ss1/8'd10; s2<=ss1%8'd10; end elseif(set_num==3) begin h1<=alarm_hours/8'd10; h2<=alarm_hours%8'd10; m1<=alarm_minutes/8'd10; m2<=alarm_minutes%8'd10; end else begin h1<=hours/8'd10; h2<=hours%8'd10; m1<=minutes/8'd10; m2<=minutes%8'd10; s1<=seconds/8'd10; s2<=seconds%8'd10; endendEndmodule6moduletop( input clk, input key1, //功能切換，按一下，秒表，再按一下設(shè)置時間，再按一下設(shè)置鬧鐘 input key2, //秒表時：開始計時；設(shè)置時間：切換分鐘和小時；鬧鐘：切換分鐘和小時 input key3, //秒表：停止計時；設(shè)置時間：時間加1；鬧鐘：時間加1 input key4, //秒表：清零計時；設(shè)置時間：時間減1；鬧鐘：時間減1 output lcd_rs, output lcd_rw, output lcd_en, output[7:0] lcd_data);wire rst;wire [3:0] set_num ;wire [1:0] set_hms_num ;wire set_start ;wire set_stop_up ;wire set_clr_down ;wire [3:0] h1 ;wire [3:0] h2 ;wire [3:0] m1 ;wire [3:0] m2 ;wire [3:0] s1 ;wire [3:0] s2 ; wire alarm_en