1、出出處處：LeeLee H H H,H, ParkPark WW H,H, RyuRyu H H G G. . HighHigh speedspeed digitaldigital hybridhybrid PLLPLL frequencyfrequency synthesizerC/synthesizerC/ MicrowaveMicrowave ConferenceConference Proceedings,Proceedings, 2005.2005. APMCAPMC 2005.2005. Asia-PacificAsia-Pacific Conference Proceedings

2、. 2006.Conference Proceedings. 2006. 鎖相技術譯文翻譯鎖相技術譯文翻譯 英文原名：英文原名：High Speed Digital Hybrid PLL FrequencyHigh Speed Digital Hybrid PLL Frequency SynthesizerSynthesizer 譯文：高速數字混合鎖相環(huán)頻率合成器譯文：高速數字混合鎖相環(huán)頻率合成器 年紀專業(yè)：年紀專業(yè)：通信工程通信工程 姓名：姓名：學號：學號： 20112011 年年 5 5 月月 2 2 日日 第1頁/共10頁 英文英文 High Speed Digital Hybrid P

3、LLHigh Speed Digital Hybrid PLL Frequency SynthesizerFrequency Synthesizer AbstractAbstract ： TheconventionalPLL(Phase locked loop) frequency synthesizer takes a long switching time because of the inherent closed-loop structure. The digital hybrid PLL (DH-PLL) which includes the open loop structure

4、into the conventionalPLLsynthesizerhasbeen studied to overcome this problem. It operates in high speed, but the hardware complexity and power consumption are other serious problems since the DLT (digital look-up table) is usually implemented by the ROMwhichcontainsthetransfer characteristic of VCO (

5、voltage controlled oscillator). This paper proposes a new DH-PLL using a very simple DLT-replacement digital logic instead of the complex ROM-type DLT. Also, a timing synchronization circuit makes the negligible overshoot and much shorter settling time for the ultra fast switching speed. Also, the h

6、ardware complexity and power consumption get decreased to about 28%, compared with the conventional DH-PLL. KeyKeyWords:Words:PLL,DLT,Frequency synthesis I. I.INTRODUCTIONINTRODUCTION High speed frequency synthesis is very important and is widely used in the electronic and communication system appli

7、cations. In 1999, El-Ela proposed that additional signal which is a synchronized saw-tooth waveform from the D/A converter is injected into the VCO input of the conventional PLL frequency synthesizer for the high speed operation 1. 中文中文 高速數字混合鎖相環(huán)頻率合成器高速數字混合鎖相環(huán)頻率合成器 摘要摘要：傳統(tǒng)的鎖相環(huán)頻率合成器需 要很長的切換時間 ,因為其內在的

8、 閉環(huán)結構。 目前已經研發(fā)的一種數字混合鎖相 環(huán)來解決這一問題在傳統(tǒng)的鎖 相環(huán)頻率合成器中加入開環(huán)結構。 它可以高速運行，但硬件復雜度和 功耗是一個嚴重的問題，因為它的 數字查找表（包含壓控振蕩器的傳 輸特性）在 ROM 中頻繁執(zhí)行。 本文提出一種新的數字混合鎖相環(huán) 使用一種簡單的數字查找表代 替復雜的 ROM 型數字查找表。 此外，定時同步電路使得環(huán)路超調 量很小且建立時間短，從而保證了 超高速切換速度。 同時,硬件復雜度和功耗比傳統(tǒng)的 數字混合鎖相環(huán)（ DH-PLL）大約降 低 28%。 關鍵詞：關鍵詞：鎖相環(huán)（PLL），數值查找 表（DLT），頻率合成 1 1 簡介簡介 高速頻率合成是一

9、種非常重要的技 術,被廣泛地應用在電子和通信系 統(tǒng)應用。 在1999年,El-Ela提出在傳統(tǒng)鎖相 環(huán)頻率合成器壓控振蕩器的輸入端 注入額外的信號從 D/A轉換器 上得到的同步鋸齒波可以使它 高速度運行【1】。 第2頁/共10頁 However, it needs the optimal slope and duration at every frequency synthesis. To get the high-speed, it is necessary to prepare the precise synchronization of the complicated design. I

10、n 2001, H. G. Ryu proposed a simplified structureoftheDDFS(directdigital frequency synthesizer)-driven PLL for the high switching speed 2. However, there is a problem that the speed of the whole system is limited by PLL. Y.FouzarproposedaPLLfrequency synthesizer of dual loop configuration using freq

11、uency-to-voltage converter (FVC) 3. It has a fast switching speed by the PD (phase detector), FVC using output signal of VCOandtheproposedcoarsetuning controller. However, H/W complexity is increased for the high switching speed. Also,itshowsthefastswitching characteristic only when the FVC works we

12、ll. Another method is pre-tuning one which is called DH-PLL in this study 4. It has very high speed switching property, but H/W complexity and power consumption are increased due to digital look-up table (DLT) which is usually implemented by the ROM including the transfer characteristic of VCO(volta

13、ge controlled oscillator). For this reason, this paper proposes a timing synchronizationcircuitfortherapid frequency synthesis and a very simple DLT replacement digital logic block instead of the complex ROM type DLT for high speed switchingand low power consumption. Also, the requisite condition is

14、 solved in the proposedmethod.Thefastswitching operation at every the frequency synthesis process is verified by the computer circuit simulation. II.II.DH-PLL synthesizerDH-PLL synthesizer 但是，該鋸齒波在每一次頻率合成 時需要最理想的斜率和持續(xù)時間。 要得到高運行速度 ,事先做好復雜 設計的精確同步是必要的。 2001年,H.G.Ryu提出了一種簡化結 構的直接數字頻率合成器 (DDFS)驅 動的高轉換速度

15、鎖相環(huán) 【2】。 但是,有一個問題,整個系統(tǒng)的速度 是受鎖相環(huán)限制的。 Y.Fouzar 提出了一種使用頻率電 壓轉換器 (FVC)具有雙重回路結構 的鎖相環(huán)頻率合成器【3】。 因為鑒相器(PD)， FVC 利用了壓控 振蕩器的輸出信號和我們提出的粗 調控制器，所以它具有快速切換速 度。 但是,因為有高速系統(tǒng)轉換速度使 得 H / W 的復雜性增加了。 另外，結果表明只有 FVC 工作狀態(tài) 良好時系統(tǒng)才有較高切換速度。 另一種方法是做預先調整也就是本 項研究中的 DH-PLL 【4】 。 它具有高速切換的特性，但是因為 數字查找表(DLT)的原因，H / W 復 雜度和功耗明顯增大了，因為DL

16、T 經常被 ROM 執(zhí)行， DLT 中包含壓控振 蕩器(VCO)的傳輸特性。 介于以上原因, 為得到較高切換速 度和低功耗，本文提出了一種新的 快速定時同步頻率合成電路，用一 個非常簡單的DLT替代數字邏輯塊， 而不用復雜的ROM型(DLT)。 同時,在該方法中所需必要條件也 解決了，頻率合成過程的高切換速 度在計算機電路仿真中已經得到驗 證了。 2.2.DH-PLL DH-PLL 合成器合成器 第3頁/共10頁 As shown in Fig.1, the open-loop synthesizer is a direct frequency synthesis type that VCO

17、generates the desired output by the FCW (frequency control word) input from the D/A converter. Thedigitalfrequencywordwhichis produced from the ROM type DLT (digital look-up table) containing the VCO transfer characteristic goes into D/A converter that generates the DC value corresponding to the des

18、ired VCO frequency. 圖1中所示的開環(huán)頻率合成技術是 一種直接頻率合成方式，在頻率控 制字（FCW）控制下VCO產生了期望 的輸出 ,VCO輸入來自于 D / A 轉換 器。 該數字頻率控制字是由 ROM類型的 包含壓控振蕩器傳輸特性的數字查 找表（DLT)產生的，進入D / A轉換 器,生成與預期的壓控振蕩器的頻 率值相對應的直流電壓。 Fig. 1. Open-loop frequency synthesizer.圖1 .開環(huán)頻率合成器。 The DC value is already found by the voltage-frequency characterist

19、ics of VCO. This open-loop frequency synthesizer has fast switching speed. However, it has the big problems of stability and sensitivity due to the inherent properties of the open loop structure. Therefore, this synthesizer type is not so attractive that this synthesizer is not widely used. 直流電壓值已經根

20、據 VCO的電壓 頻率特性建立了。 該開環(huán)頻率合成器具有高切換速 度。 但是, 由于開環(huán)結構的固有特性 , 該頻率合成器在穩(wěn)定性和靈敏度方 面還有比較大的問題。 因此,這種合成器類型缺乏吸引力 , 該合成器沒有廣泛應用。 第4頁/共10頁 Fig. 2. Closed-loop PLL frequency synthesizer.圖 2.閉合回路PLL 頻率合成器。 In Fig. 2, FCW (frequency control word) is the division ratio command for frequency synthesis. This structure is ve

21、ry popular and excellent in the aspects of the stability, variety and flexibility. Also, the spurious noise is smaller than other frequency synthesizer. It takes the longer acquisition time to jump into a new frequency so that the switching speed is low. Theswitchingtimegetslongerasthe generation fr

22、equency spacing is increased. DH-PLL frequency synthesizer is shown in Fig.3. 在圖2中，頻率控制字（ FCW）為頻 率合成分頻比控制指令。 這種結構在穩(wěn)定度、多樣性和適應 性方面是非常流行、優(yōu)良的。 同時，寄生噪音是比其他的頻率合 成器要小。 它需要較長的捕獲時間來跳變?yōu)橐?個新的頻率，因而切換速度低。 如果當前頻率與生成頻率的間隔增 加時，系統(tǒng)切換時間也增加了。 DH-PLL頻率合成器如圖3所示。 Fig.3.DH-PLL using DLT (digital look-up table).圖3.采用數字查表（DL

23、T）的DH-PLL。 The open-loop structure of the DLT and DAC is combined into the conventional PLL closed-loop structure. In the conventional PLL, the output voltage of LF is fed to the VCO. On the contrary, sum of DAC output voltage and the LF output voltage drives the VCO whenever FCW is changed. Therefo

24、re, unlike conventional PLL, DAC outputs the steady state driving voltage at every new FCW change times so that high speed frequency switching may be possible. However, the DH-PLL has a serious problem of the phase change at every new frequency synthesis. DLT開環(huán)結構和DAC組合成傳統(tǒng)的鎖 相環(huán)閉環(huán)結構。 在傳統(tǒng)鎖相環(huán)中 ,輸出的低頻電壓

25、反饋到壓控振蕩器。 相反,每當FCW改變，DAC輸出電壓的 總和與低頻輸出電壓一起驅動壓控 振蕩器。 因此,與傳統(tǒng)的鎖相環(huán)不同，每當 FCW更新時，該鎖相環(huán)的 DAC能輸出 電壓的穩(wěn)定的驅動壓，所以,高速頻 率切換就可以實現。 但是,在進行一個新頻率合成時， DH-PLL有一個嚴重的相位變化的問 題。 第5頁/共10頁 As shown in Fig. 4, the overshoot and the settling time have a trade-off relationship because the output of programmable divider moves into

26、 other point after the new FCW start, even though system parameters are previously optimized. So, it has a long settling time and the switching speed gets down. Phase detector inputs are，waveforms of Fig.4 which are used for the control voltage of LF(loop filter). Therefore, the relationship between

27、 and is fixed until a new FCW is made. 如圖4中所示,超調量和建立時間有 一種互為消長關系,因為 FCW更新 后，可編程除法器的輸出漂移到另 一個值,盡管系統(tǒng)參數的是預先優(yōu) 化的。 所以,它需要較長的穩(wěn)定時間，切換 速度也降低了。 鑒相器的輸入為圖4中所示的， 號波形，是低通濾波器（ LF）的控 制電壓。 因此,在FCW更新前波形之間的 關系是固定的。 Fig. 4. Operating signal of DH-PLL.圖4 DH-PLL工作信號 However, ifanewFCWistriggered, waveform goes down the

28、low-state (0) in unexpected place, which means a voltage change start of LF. Though there is a steady state voltage from the DAC, the overshoot happens for a new frequency synthesis so that settling process takes a long time. Like the conventional PLL, the overshoot and settling time get greatly cha

29、nged for the wider frequency synthesis spacing. In order to overcome this problem, a new timing synchronization circuit is additionally designed and the whole DH-PLL structure is shown in Fig.5. 但是,如果觸發(fā)了一個新 FCW,波 形將在出乎意料的位置下降到低電 平狀態(tài)(“0”）,這意味著LF的電壓開 始發(fā)生變化。 雖然DAC輸出穩(wěn)定的電壓 ,但是當進 行一個新的頻率合成時會出現超調 現象,因而穩(wěn)定過程

30、需要較長時間。 與傳統(tǒng)的鎖相環(huán)相似 ,因為更寬的 頻率合成間距，超調量和穩(wěn)定時間 變化很大。 為了克服這一問題 ,我們另外設計 了一種新的定時同步電路 ,完整的 DH-PLL結構如圖5所示。 第6頁/共10頁 Fig.5.Blockdiagramofthenewproposed DH-PLL. 圖5新提出的DH-PLL框圖。 IV. Simulation results andIV. Simulation results and discussiondiscussion In this paper, parameters of table 1 and procedure of table 2

31、are used to verify the switching function of the proposed DH-PLL circuit structure. FCW is the division ratio. Fig. 9 and 10 are theresultsofthecomputercircuit simulations. Division ratio is 8 bit binary value and FCW changes in every 1 msec. Change of the division ratio should be made in the linear

32、 region of VCO transfer curve. In Fig.10, the upper waveform is input driving voltage of VCO, and the lower is output voltage of DAC. As shown in Fig.10, there are very small overshoot and very short settling time in the frequencysynthesistransitionprocess because the input to the phase detector is

33、synchronized with the reference input signal irrespective of how many the programmable divider counts the VCO output. 三三 仿真結果與討論仿真結果與討論 在本文中 ,表1的參數和表 2中的步 驟是用來檢驗我們提出了 DH-PLL的 電路結構的切換功能。 FCW是分頻比。圖9和10是計算機電 路模擬的結果。 分頻比是8bit的2進制數，FCW變化 率為1/ms。 分頻比的變化范圍應該控制在VCO 的線性范圍內。 在圖10中，上面的波形VCO的輸入驅 動電壓，下面的波形是DAC的輸

34、出電 壓。 如圖10所示，因為鑒相器的輸入與 參考輸入信號同步，與可編程除法 器對VCO輸出的計算值多少無關，所 以該系統(tǒng)在頻率合成過渡過程中超 調量很小，穩(wěn)定時間較小。 第7頁/共10頁 Output voltage of DAC is 0 V at the initial state. Consequently, voltage from DAC and loop filter output are added to drive the VCO so that the desired frequency may be obtained. It can be easily shown tha

35、t the input driving voltageofVCOisdifferentfromthe conventional PLL closed-loop structure at the switching times. It is swiftly changed by output voltage of DAC and moved into the steady state driving voltage in a very shorter time whenever FCW varies. From these results, it is shown that DHPLL has

36、very high speed switching function. Also,wecancomparetheproposed DLT-replacementblockwiththe conventional ROM type DLT in the aspects of the circuit complexity. DAC在初始狀態(tài)的輸出電壓是0V。 因此,DAC和環(huán)路濾波器的輸出電壓 相加后，驅動壓控振蕩器,這樣就可 以獲得所需的頻率。 顯然，在頻率切換階段，該系統(tǒng)的 VCO的輸入驅動電壓是不同傳統(tǒng) PLL 的閉環(huán)結構的。 一旦FCW改變，VCO的輸入將會隨著 DAC輸出改變而迅速改變，

37、在短時間 內跳變到一個穩(wěn)定的驅動電壓狀 態(tài)。 根據以上結果,表明DHPLL具有超高 速切換功能。 而且,可以把我們提出的 DLT替代組 件與傳統(tǒng)的ROM類型DLT在電路的復 雜性方面進行比較。 表 1 仿真參數 表 2 仿真過程 第8頁/共10頁 V. ConclusionV. Conclusion In this paper, a DH-PLL synthesizer using simple digital logic circuit instead of ROM type DLT block is proposed to overcome the circuit complexity a

38、nd power consumption of the conventional DH-PLL. In fact, DLT block is a burden of hardware complexity and takes a long access time to speeddowntheswitchingoperation. In addition, there is a necessary condition that the first frequency control word should be same at the initial operation. So, the pr

39、oposedstructuresolvestherequisite conditionandisverifiedbycomputer simulation. Thehardwarecomplexityandpower consumption gets decreased to about 28%, as compared with the conventional DH-PLL. Frequencysynthesizeroftheproposed DH-PLL structure can be used for the fast frequency hopping system, electronic and 圖 10 壓控振蕩器驅動電壓波形、DAC 輸 出電壓 四四 結論結論 本文提出了一種使用簡單的數字邏 輯電路代替 ROM型(DLT)的DH-PLL合 成器，以克服電路復雜度和傳統(tǒng) DH-PLL的功耗。 事實上,數字查