1、ic制造流程簡(jiǎn)介,基本概念,半導(dǎo)體是指導(dǎo)電能力介于導(dǎo)體和絕緣體之間的材料，其指四價(jià)硅中添加三價(jià)或五價(jià)化學(xué)元素而形成的電子元件，它有方向性，可以用來制造邏輯線路使電路具有處理資訊的功能。 半導(dǎo)體的傳導(dǎo)率可由攙雜物的濃度來控制：攙雜物的濃度越高，半導(dǎo)體的電阻系數(shù)就越低。 p型半導(dǎo)體中的多數(shù)載體是電洞。硼是p型的摻雜物。 n型半導(dǎo)體的多數(shù)載體是電子。磷，砷，銻是n型的攙雜物。 集成電路（ic) 是指把特定電路所需的各種電子元件及線路縮小并制作在大小僅及2平方公分或更小的面積上的一種電子產(chǎn)品。 集成電路主要種類有兩種：邏輯logic及記憶體memory。前者主要執(zhí)行邏輯的運(yùn)算如電腦的微處理器后者則如只

2、讀器read only 及隨機(jī)處理器random access memory等。,集成電路(ic)產(chǎn)業(yè)主要分為設(shè)計(jì)生產(chǎn)測(cè)試 封裝四個(gè)階段. 集成電路的生產(chǎn)主要分三個(gè)階段：,基本概念,基本制程,基本制程,原理：在晶片表面上覆上一層感光材料，來自光源的平行光透過光罩的圖形，使得晶片表面的感光材料進(jìn)行選擇性的感光。 感光材料：正片經(jīng)過顯影(development)，材料所獲得的圖案與光罩上相同稱為正片。負(fù)片如果彼此成互補(bǔ)的關(guān)係稱負(fù)片,微影制程 -1,微影制程 -2,摻雜物(doping)概念: to get the extrinsic semiconductor by adding donors o

3、r acceptors, which may cause the impurity energy level. the action that adding particular impurities into the semiconductor is called “doping” and the impurity that added is called the “dopant”.,doping介紹,doping 方法: 1. 擴(kuò)散（diffusion） 2. 離子植入（implantation）,pre-deposition: 將摻雜物置于wafer表面. generally used

4、dopant resource furnace design:,carrier gas,heater,石英管,solid dopant source furnace,o2,liquid dopant source,carrier gas,gas dopant source,valve,o2,(a),(c),(b),擴(kuò)散制程（diff) -1,solid dopant source,drive-in: to implant the dopant into the wafer by the thermal process,擴(kuò)散制程（diff) -2,1. the definition: a man

5、ufacturing process that can uniformly implants the ions into the wafer in the specified depth and consistence by selecting and accelerating ions. 2. the purpose: to change the resistance value of the semiconductor by implanting the dopant. 3. energy range (8 years ago) (1) general process：10 kev - 1

6、80 kev (0.35m) (100kev for 0.18 m now) (2) advanced process：10 kev - 3 mev (0.5m) (3) r&d process：0.2 kev - 5 kev,離子植入制程(imp) -1,dopant source,ion source,mass analysis,accelerator,scanner,electron shower,extractor,farady cap,離子植入制程(imp) -2,parameters doping elementsselection scanning uniformity cont

7、rol temperature control concentration control,factors the selection of the ion resource the design of the mass analyzer scanning system vacuum control precise wafer position control preciseand stable electric power supplier the measurement of the ion current (farady cup),doping參數(shù),dc,metal target,gas

8、 in,to the vacuum pump,wafer,plate,collimator,pvd制程,(a) reagents diffuse through the interface boundary layer (b) adsorbed onto the wafer surface (c) deposition reaction happens (d) byproducts diffuse through the interface boundary layer (e) reagents & byproducts pass away,heat source,(a) (d) (b) (c

9、),(e),reaction,main stream interface boundary layer wafer surface,vacuum system,cvd制程,(1) thermal oxidation the growth temperature is above 900 0c. high quality sio2. (2) low pressure cvd (lpcvd) the growth temperature is around 400 0c to 750 0c. better step coverage ability. (3) plasma enhanced cvd

10、 (pecvd) the growth temperature is under 400 0c. in the case of the al deposition and non-thermal process.,solutions to deposition,down force,wafer,wafer carrier,carrier film,slurry,carrier,wafer,interconnects,composite pad,table,polishing pad,polishing table,p,cmp system schematic,carrier film,c,ma

11、jor parameters in cmp,sio2 cmp: down force rotating speed (p) type of the pad metal and si cmp: ph measurement,* the lower the force-speed ratio the better the planarity,slurry,particle (0.1 2.0 um) silica (colloidal) alumina (dispersed) liquor (contains some oxidant and organic reagents in the case

12、 of metal cmp) koh nh4oh,wafer cleaning,purpose: to remove the remainsand impuriti雜質(zhì),methods: brush cleaning spray cleaning ultrasonic 超聲波cleaning,photo resist,sio2,si substrate,photomask,positive積極 resist,negative負(fù)值 resist,etching intro - 1,next page,positive resist,negative resist,etching intro -

13、2,continue,etching methods,wet etching (isotropic) relatively simple process high throughput low quality dry etching (anisotropic) high quality (due to the excellent pattern transfer ability) worse selectivity,wet etching,substrate,thin film,solution,boundary layer,reagent,resultant,reaction,photo r

14、esist,(a) isotropic etching：a=0 (erh=erv),(b) anisotropic etching：a=1 (erh=0),isotropic & anisotropic,isotropic,quartz dome,silicon wafer,silicon carbide coated graphite,rf coil,gas in,gas exit,silicon carbide susceptor,gas exit,silicon wafers,rf induction heating coil,dry etching system - 1,(a) spu

15、ttering etching,(b) plasma etching,(c) reactive ion etching,ion,reactive ion,volatile product,volatile product,reactive ion,rie,scheme diagram of rie system,gas in,to vacuum pump,plasma,electrode,rf,annealing,sio2 post ion implantation annealing,rtp rapid thermal process 快速升溫過程,furnace,reaction room,gas in (h2),wafer,3-zone heating element,gas out,gas in (o2),loading area,rapid thermal processin