1、第六章 Verilog HDL高級程序設(shè)計舉例,8/2/2020,1,Microelectronics School Xidian University,6.1數(shù)字電路系統(tǒng)設(shè)計的層次化描述方法,Bottom-Up:,8/2/2020,2,Microelectronics School Xidian University,串行加法器: 一個四位串行加法器由4個全加器構(gòu)成。全加器是串行加法器的子模塊，而全加器是由基本的邏輯門構(gòu)成，這些基本的邏輯門就是所說的葉子模塊。這個設(shè)計中運(yùn)用葉子模塊（基本邏輯門）搭建成子模塊（全加器），再用子模塊搭建成所需要的電路（串行加法器）。 顯然，Bottom-Up的設(shè)

2、計方法沒有明顯的規(guī)律可循，主要依靠設(shè)計者的實(shí)踐經(jīng)驗(yàn)和熟練的設(shè)計技巧，用逐步試探的方法最后設(shè)計出一個完整的數(shù)字系統(tǒng)。系統(tǒng)的各項性能指標(biāo)只有在系統(tǒng)構(gòu)成后才能分析測試。此種設(shè)計方法常用于原理圖的設(shè)計中，相比于其它方法此種方法對于實(shí)現(xiàn)各個子模塊電路所需的時間較短。,8/2/2020,3,Microelectronics School Xidian University,Top-Down:,8/2/2020,4,Microelectronics School Xidian University,使用Top-Down設(shè)計方法對一個典型cpu進(jìn)行設(shè)計：,8/2/2020,5,Microelectronics

3、 School Xidian University,向量點(diǎn)積乘法器： 采用模塊層次化設(shè)計方法，設(shè)計4維向量點(diǎn)積乘法器，其中向量a=（a1，a2，a3，a4）；b=（b1，b2，b3，b4）。點(diǎn)積乘法規(guī)則為：,8/2/2020,6,Microelectronics School Xidian University,8/2/2020,7,Microelectronics School Xidian University,Verilog HDL程序代碼為： module vector(a1,a2,a3,a4,b1,b2,b3,b4,out); input 3:0 a1,a2,a3,a4,b1,b2,

4、b3,b4; output 9:0 out; wire 7:0 out1,out2,out3,out4; wire 8:0 out5, out6; wire 9:0 out; mul_addtree U1(.x(a1),.y(b1),.out(out1) ; mul_addtree U2(.x(a2),.y(b2),.out(out2) ; mul_addtree U3(.x(a3),.y(b3),.out(out3) ; mul_addtree U4(.x(a4),.y(b4),.out(out4) ; add #(8) U5(.a(out1),.b(out2),.out(out5); ad

5、d #(8) U6(.a(out3),.b(out4),.out(out6); add #(9) U7(.a(out5),.b(out6),.out(out); endmodule / adder module add(a,b,out); parameter size=8; input size-1:0 a,b; output size:0 out; assign out=a+b; endmodule,/Multiplier module mul_addtree(mul_a,mul_b,mul_out); input 3:0 mul_a,mul_b; / IO declaration outp

6、ut 7:0 mul_out; wire 3:0 mul_out; /Wire declaration wire 3:0 stored0,stored1,stored2,stored3; wire 3:0 add01, add23; assign stored3=mul_b3?1b0,mul_a,3b0:8b0; /Logic design assign stored2=mul_b2?2b0,mul_a,2b0:8b0; assign stored1=mul_b1?3b0,mul_a,1b0:8b0; assign stored0=mul_b0?4b0,mul_a:8b0; assign ad

7、d01=stored1+stored0; assign add23=stored3+stored2; assign mul_out=add01+add23; endmodule,6.2典型電路設(shè)計,6.2.1加法器樹乘法器 加法器樹乘法器的設(shè)計思想是“移位后加”，并且加法運(yùn)算采用加法器樹的形式。乘法運(yùn)算的過程是，被乘數(shù)與乘數(shù)的每一位相乘并且乘以相應(yīng)的權(quán)值，最后將所得的結(jié)果相加，便得到了最終的乘法結(jié)果。 例：下圖是一個4位的乘法器結(jié)構(gòu)，用Verilog HDL設(shè)計一個加法器樹4位乘法器,8/2/2020,8,Microelectronics School Xidian University,8/

8、2/2020,9,Microelectronics School Xidian University,module mul_addtree(mul_a,mul_b,mul_out); input 3:0 mul_a,mul_b; / IO declaration output 7:0 mul_out; wire 7:0 mul_out; /Wire declaration wire 7:0 stored0,stored1,stored2,stored3; wire 7:0 add01, add23; assign stored3=mul_b3?1b0,mul_a,3b0:8b0; /Logic

9、 design assign stored2=mul_b2?2b0,mul_a,2b0:8b0; assign stored1=mul_b1?3b0,mul_a,1b0:8b0; assign stored0=mul_b0?4b0,mul_a:8b0; assign add01=stored1+stored0; assign add23=stored3+stored2; assign mul_out=add01+add23; endmodule,module mult_addtree_tb; reg 3:0mult_a; reg 3:0mult_b; wire 7:0mult_out; / m

10、odule instance mul_addtree U1(.mul_a(mult_a),.mul_b(mult_b),.mul_out(mult_out); initial /Stimuli signal begin mult_a=0; mult_b=0; repeat(9) begin #20 mult_a=mult_a+1; mult_b=mult_b+1; end end endmodule,流水線結(jié)構(gòu),例：下圖是一個4位的乘法器結(jié)構(gòu)，用Verilog HDL設(shè)計一個兩級流水線加法器樹4位乘法器。 兩級流水線加法器樹4位乘法器結(jié)構(gòu)如圖所示，通過在第一級與第二級、第二級與第三級加法器之間

11、插入D觸發(fā)器組，可以實(shí)現(xiàn)兩級流水線設(shè)計。,8/2/2020,10,Microelectronics School Xidian University,8/2/2020,11,Microelectronics School Xidian University,module mul_addtree_2_stage(clk,clr,mul_a,mul_b,mul_out); input clk,clr; input 3:0 mul_a,mul_b; / IO declaration output 7:0 mul_out; reg 7:0 add_tmp_1,add_tmp_2,mul_out; wi

12、re 7:0 stored0,stored1,stored2,stored3; assign stored3=mul_b3?1b0,mul_a,3b0:8b0; /Logic design assign stored2=mul_b2?2b0,mul_a,2b0:8b0; assign stored1=mul_b1?3b0,mul_a,1b0:8b0; assign stored0=mul_b0?4b0,mul_a:8b0; always(posedge clk or negedge clr) /Timing control begin if(!clr) begin add_tmp_1=8b00

13、00_0000; add_tmp_2=8b0000_0000; mul_out=8b0000_0000; end else begin add_tmp_1=stored3+stored2; add_tmp_2=stored1+stored0; mul_out=add_tmp_1+add_tmp_2; end end endmodule,8/2/2020,12,Microelectronics School Xidian University,module mult_addtree_2_stag_tb; reg clk, clr; reg 3:0mult_a, mult_b; wire 7:0m

14、ult_out; mul_addtree_2_stage U1(.mul_a(mult_a),.mul_b(mult_b), .mul_out(mult_out),.clk(clk),.clr(clr); initial begin clk=0; clr=0; mult_a=1; mult_b=1; #5 clr=1; end always #10 clk=clk; initial begin repeat(5) begin #20 mult_a=mult_a+1; mult_b=mult_b+1; end end endmodule,6.2.2 Wallace 樹乘法器,Wallace樹乘法

15、器運(yùn)算原理如下圖所示，其中FA為全加器HA為半加器。其基本原理是，加法從數(shù)據(jù)最密集的地方開始，不斷地反復(fù)使用全加器半加器來覆蓋“樹”。這一級全加器是一個3輸入2輸出的器件，因此全加器又稱為3-2壓縮器。通過全加器將樹的深度不斷縮減，最終縮減為一個深度為2的樹。最后一級則采用一個簡單的兩輸入加法器組成。,8/2/2020,13,Microelectronics School Xidian University,8/2/2020,14,Microelectronics School Xidian University,module wallace(x,y,out); parameter size=

16、4; / Define parameters input size-1:0 x,y; output 2*size-1:0 out;/ IO declaration wire size*size-1:0 a; wire 1:0 b0,b1,c0,c1,c2,c3; /Wire declaration wire 5:0 add_a,add_b; wire 6:0 add_out; wire 2*size-1:0 out;,8/2/2020,15,Microelectronics School Xidian University,assign a=x3,x3,x2,x2,x1,x3,x1,x0,x3

17、,x2,x1,x0,x2,x1,x0,x0 endmodule,module fadd(x, y, z, out); output 1:0out; input x,y, z; assign out=x+y+z; endmodule,module hadd(x, y, out); output 1:0out; input x,y; assign out=x+y; endmodule,8/2/2020,16,Microelectronics School Xidian University,module wallace_tb; reg 3:0 x, y; wire 7:0 out; wallace

18、 m(.x(x),.y(y),.out(out); / module instance initial / Stimuli signal begin x=3; y=4; #20 x=2; y=3; #20 x=6; y=8; end endmodule,6.2.3復(fù)數(shù)乘法器 復(fù)數(shù)乘法的算法是：設(shè)復(fù)數(shù) ，則復(fù)數(shù)乘法結(jié)果 復(fù)數(shù)乘法器的電路結(jié)構(gòu)如下圖所示。將復(fù)數(shù)x的實(shí)部與復(fù)數(shù)y的實(shí)部相乘，減去x的虛部與y的虛部相乘，得到輸出結(jié)果的實(shí)部。將x的實(shí)部與y的虛部相乘，加上x的虛部與y的實(shí)部相乘，得到輸出結(jié)果的虛部。,8/2/2020,17,Microelectronics School Xidian Un

19、iversity,8/2/2020,18,Microelectronics School Xidian University,module complex(a,b,c,d,out_real,out_im); input 3:0a,b,c,d; output 8:0 out_real,out_im; wire 7:0 sub1,sub2,add1,add2; wallaceU1(.x(a),.y(c),.out(sub1); wallace U2(.x(b),.y(d),.out(sub2); wallace U3(.x(a),.y(d),.out(add1); wallace U4(.x(b)

20、,.y(c),.out(add2); assignout_real=sub1-sub2; assign out_im = add1+ add2; endmodule module complex_tb; reg 3:0 a, b,c,d; wire 8:0 out_real; wire 8:0 out_im; complex U1(.a(a),.b(b),.c(c),.d(d),.out_real(out_real),.out_im(out_im);,initial begin a=2; b=2; c=5; d=4; #10 a=4; b=3; c=2; d=1; #10 a=3; b=2;

21、c=3; d=4; end endmodule,6.2.4 FIR濾波器設(shè)計,有限沖激響應(yīng)（FIR）濾波器就是一種常用的數(shù)字濾波器，采用對已輸入樣值的加權(quán)和來形成它的輸出。其系統(tǒng)函數(shù)為 其中z-1表示延時一個時鐘周期，z-2表示延時兩個時鐘周期。 對于輸入序列Xn的FIR濾波器可用下圖所示的結(jié)構(gòu)示意圖來表示，其中Xn是輸入數(shù)據(jù)流。各級的輸入連接和輸出連接被稱為抽頭，并且系數(shù)（b0,b1,bn）被稱為抽頭系數(shù)。一個M階的FIR濾波器將會有M+1個抽頭。通過移位寄存器用每個時鐘邊沿n（時間下標(biāo)）處的數(shù)據(jù)流采樣值乘以抽頭系數(shù)，并將它們加起來形成輸出Yn。,8/2/2020,19,Microelect

22、ronics School Xidian University,8/2/2020,20,Microelectronics School Xidian University,module FIR (Data_out,Data_in,clock,reset); output 9:0 Data_out; input 3:0 Data_in; input clock,reset; wire 9:0 Data_out; wire 3:0 samples_0,samples_1,samples_2,samples_3,samples_4, samples_5,samples_6,samples_7,sam

23、ples_8; shift_register U1(.Data_in(Data_in),.clock(clock),.reset(reset), .samples_0(samples_0),.samples_1(samples_1), .samples_2(samples_2),.samples_3(samples_3), .samples_4(samples_4),.samples_5(samples_5), .samples_6(samples_6),.samples_7(samples_7), .samples_8(samples_8); caculator U2(.samples_0(

24、samples_0),.samples_1(samples_1), .samples_2(samples_2),.samples_3(samples_3), .samples_4(samples_4),.samples_5(samples_5), .samples_6(samples_6),.samples_7(samples_7), .samples_8(samples_8),.Data_out(Data_out); endmodule,8/2/2020,21,Microelectronics School Xidian University,module shift_register(Da

25、ta_in,clock,reset,samples_0,samples_1,samples_2, samples_3,samples_4,samples_5,samples_6, samples_7,samples_8); input 3:0 Data_in; input clock,reset; output 3:0 samples_0,samples_1,samples_2,samples_3,samples_4, samples_5,samples_6,samples_7,samples_8; reg 3:0 samples_0,samples_1,samples_2,samples_3

26、,samples_4, samples_5,samples_6,samples_7,samples_8; always(posedge clock or negedge reset) begin if(reset) begin samples_0=4b0; samples_1=4b0; samples_2=4b0; samples_3=4b0; samples_4=4b0; samples_5=4b0; samples_6=4b0; samples_7=4b0; samples_8=4b0; end,8/2/2020,22,Microelectronics School Xidian Univ

27、ersity,else begin samples_0=Data_in; samples_1=samples_0; samples_2=samples_1; samples_3=samples_2; samples_4=samples_3; samples_5=samples_4; samples_6=samples_5; samples_7=samples_6; samples_8=samples_7; end end endmodule module caculator(samples_0,samples_1,samples_2,samples_3,samples_4,samples_5,

28、samples_6, samples_7,samples_8,Data_out); input 3:0 samples_0,samples_1,samples_2,samples_3,samples_4,samples_5,samples_6, samples_7,samples_8; output 9:0 Data_out; wire 9:0 Data_out; wire 3:0 out_tmp_1,out_tmp_2,out_tmp_3,out_tmp_4,out_tmp_5; wire 7:0 out1,out2,out3,out4,out5;,8/2/2020,23,Microelec

29、tronics School Xidian University,parameter b0=4b0010; parameter b1=4b0011; parameter b2=4b0110; parameter b3=4b1010; parameter b4=4b1100; mul_addtree U1(.mul_a(b0),.mul_b(out_tmp_1),.mul_out(out1); mul_addtree U2(.mul_a(b1),.mul_b(out_tmp_2),.mul_out(out2); mul_addtree U3(.mul_a(b2),.mul_b(out_tmp_3

30、),.mul_out(out3); mul_addtree U4(.mul_a(b3),.mul_b(out_tmp_4),.mul_out(out4); mul_addtree U5(.mul_a(b4),.mul_b(samples_4),.mul_out(out5); assign out_tmp_1=samples_0+samples_8; assign out_tmp_2=samples_1+samples_7; assign out_tmp_3=samples_2+samples_6; assign out_tmp_4=samples_3+samples_5; assign Dat

31、a_out=out1+out2+out3+out4+out5; endmodule,8/2/2020,24,Microelectronics School Xidian University,module FIR_tb; reg clock,reset; reg 3:0 Data_in; wire 9:0 Data_out; FIRU1 (.Data_out(Data_out),.Data_in(Data_in),.clock(clock),.reset(reset); initial begin Data_in=0; clock=0; reset=1; #10 reset=0; end al

32、ways begin #5 clock=clock; #5 Data_in=Data_in+1; end endmodule,6.2.5片內(nèi)存儲器的設(shè)計,（1）RAM的Verilog HDL描述 RAM是隨機(jī)存儲器，存儲單元的內(nèi)容可按需隨意取出或存入。這種存儲器在斷電后將丟失掉所有數(shù)據(jù)，一般用來存儲一些短時間內(nèi)使用的程序和數(shù)據(jù)。其內(nèi)部結(jié)構(gòu)如下圖所示：,8/2/2020,25,Microelectronics School Xidian University,例：用Verilog HDL設(shè)計深度為8，位寬為8的單端口RAM。 單口RAM，只有一套地址總線，讀操作和寫操作是分開的。,8/2/202

33、0,26,Microelectronics School Xidian University,module ram_single( clk, addm, cs_n, we_n, din, dout); input clk; /clock signal input 2:0 addm; /address signal input cs_n; /chip select signal input we_n; /write enable signal input 7:0 din;/ input data output7:0 dout;/ output data reg 7:0 dout; reg 7:0

34、 raml 7:0; /8*8 bites register always(posedge clk) begin if(cs_n) dout=8bzzzz_zzzz; else if(we_n) /read data dout=ramladdm; else /write data ramladdm=din; end endmodule,8/2/2020,27,Microelectronics School Xidian University,module ram_single_tb; reg clk, we_n, cs_n; reg 2:0addm; reg 7:0din; wire 7:0d

35、out; ram_single U1(.clk(clk),.addm(addm),.cs_n(cs_n),.we_n(we_n), .din(din),.dout(dout); initial begin clk=0; addm=0; cs_n=1; we_n=0; din=0; #5 cs_n=0; #315 we_n=1; end always #10 clk=clk; initial begin repeat(7) begin #40 addm=addm+1; din=din+1; end #40 repeat(7) #40 addm=addm-1; end endmodule,例：用V

36、erilog HDL設(shè)計深度為8，位寬為8的雙端口RAM。 雙口RAM具有兩套地址總線，一套用于讀數(shù)據(jù)，另一套用于寫數(shù)據(jù)。 二者可以分別獨(dú)立操作。,8/2/2020,28,Microelectronics School Xidian University,module ram_dual(q, addr_in, addr_out, d, we, rd, clk1, clk2); output 7:0 q; /output data input 7:0 d; /input data input 2:0 addr_in; /write data address signal input 2:0 ad

37、dr_out; /output data address signal input we; /write data control signal input rd; /read data control signal input clk1; /write data clock input clk2; /read data clock reg 7:0 q; reg 7:0 mem7:0; /8*8 bites register always(posedge clk1) begin if(we) memaddr_in=d; end,always(posedge clk2) begin if(rd)

38、 q=memaddr_out; end endmodule,8/2/2020,29,Microelectronics School Xidian University,module ram_dual_tb; reg clk1, clk2, we, rd; reg 2:0addr_in; reg 2:0addr_out; reg 7:0d; wire 7:0q; ram_dual U1(.q(q),.addr_in(addr_in),.addr_out(addr_out),.d(d),.we(we), .rd(rd),.clk1(clk1),.clk2(clk2); initial begin

39、clk1=0; clk2=0; we=1; rd=0; addr_in=0; addr_out=0; d=0; #320 we=0; rd=1; end always begin #10 clk1=clk1; clk2=clk2; end,initial begin repeat(7) begin #40 addr_in=addr_in+1; d=d+1; end #40 repeat(7) #40 addr_out=addr_out+1; end endmodule,（2）ROM的Verilog HDL描述 ROM即只讀存儲器，是一種只能讀出事先存儲的數(shù)據(jù)的存儲器，其特性是存入數(shù)據(jù)無法改變，

40、也就是說這種存儲器只能讀不能寫。由于ROM在斷電之后數(shù)據(jù)不會丟失，所以通常用在不需經(jīng)常變更資料的電子或電腦系統(tǒng)中，資料并不會因?yàn)殡娫搓P(guān)閉而消失。,8/2/2020,30,Microelectronics School Xidian University,module rom(dout, clk, addm, cs_n); input clk, cs_n; input 2:0 addm; output 7:0 dout; reg 7:0 dout; reg 7:0 rom7:0; initial begin rom0=8b0000_0000; rom1=8b0000_0001; rom2=8b0

41、000_0010; rom3=8b0000_0011; rom4=8b0000_0100; rom5=8b0000_0101;,8/2/2020,31,Microelectronics School Xidian University,rom6=8b0000_0110; rom7=8b0000_0111; end always(posedge clk) begin if(cs_n) dout=8bzzzz_zzzz; elsedout=romaddm; end endmodule module rom_tb; reg clk, cs_n; reg 2:0addm; wire 7:0dout;

42、rom U1(.dout(dout),.clk(clk),.addm(addm),.cs_n(cs_n); initial begin clk=0; addm=0; cs_n=0; end always #10 clk=clk; initial begin repeat(7) #20 addm=addm+1; end endmodule,6.2.6 FIFO設(shè)計,FIFO（First In First Out）是一種先進(jìn)先出的數(shù)據(jù)緩存器，通常用于接口電路的數(shù)據(jù)緩存。與普通存儲器的區(qū)別是沒有外部讀寫地址線，可以使用兩個時鐘分別進(jìn)行寫和讀操作。FIFO只能順序?qū)懭霐?shù)據(jù)和順序讀出數(shù)據(jù)，其數(shù)據(jù)地址由內(nèi)

43、部讀寫指針自動加1完成，不能像普通存儲器那樣可以由地址線決定讀取或?qū)懭肽硞€指定的地址。 FIFO由存儲器塊和對數(shù)據(jù)進(jìn)出FIFO的通道進(jìn)行管理的控制器構(gòu)成，每次只對一個寄存器提供存取操作，而不是對整個寄存器陣列進(jìn)行。FIFO有兩個地址指針，一個用于將數(shù)據(jù)寫入下一個可用的存儲單元，一個用于讀取下一個未讀存儲單元的操作。讀寫數(shù)據(jù)必須一次進(jìn)行。,8/2/2020,32,Microelectronics School Xidian University,其讀寫過程如下圖所示：,8/2/2020,33,Microelectronics School Xidian University,當(dāng)一個堆棧為空時（圖

44、A），讀數(shù)據(jù)指針和寫數(shù)據(jù)指針都指向第一個存儲單元，如所示；當(dāng)寫入一個數(shù)據(jù)時（圖 B）寫數(shù)據(jù)指針將指向下個存儲單元；經(jīng)過七次寫數(shù)據(jù)操作后（圖 C）寫指針將指向最后一個數(shù)據(jù)單元；當(dāng)經(jīng)過連續(xù)八次寫操作之后寫指針將回到首單元并且顯示堆棧狀態(tài)為滿（圖 D）。數(shù)據(jù)的讀操作和寫操作相似，當(dāng)讀出一個數(shù)據(jù)時，讀數(shù)據(jù)指針將移向下一個存儲單元，直到讀出全部的數(shù)據(jù)，此時讀指針回到首單元，堆棧狀態(tài)顯示為空。,一個FIFO的組成一般包括兩個部分：地址控制部分和存儲數(shù)據(jù)的RAM部分。如下圖所示。地址控制部分可以根據(jù)讀寫指令生成RAM地址。RAM用于存儲堆棧數(shù)據(jù)，并根據(jù)控制部分生成的地址信號進(jìn)行數(shù)據(jù)的存儲和讀取操作。這里的R

45、AM采用的是前面提到的雙口RAM。,8/2/2020,34,Microelectronics School Xidian University,8/2/2020,35,Microelectronics School Xidian University,例：用Verilog HDL設(shè)計深度為8，位寬為8的FIFO /頂層模塊： module FIFO_buffer(clk,rst,write_to_stack,read_from_stack,Data_in,Data_out); input clk,rst; input write_to_stack,read_from_stack; input

46、7:0 Data_in; output 7:0 Data_out; wire 7:0Data_out; wire stack_full, stack_empty; wire 2:0 addr_in, addr_out; FIFO_control U1(.stack_full(stack_full),.stack_empty(stack_empty), .write_to_stack(write_to_stack),.write_ptr(addr_in), .read_ptr(addr_out),.read_from_stack(read_from_stack), .clk(clk),.rst(

47、rst); ram_dual U2(.q(Data_out),.addr_in(addr_in),.addr_out(addr_out), .d(Data_in),.we(write_to_stack),.rd(read_from_stack), .clk1(clk),.clk2(clk); endmodule,8/2/2020,36,Microelectronics School Xidian University,/控制模塊： module FIFO_control( write_ptr, read_ptr, stack_full, stack_empty, write_to_stack,

48、 read_from_stack, clk, rst); parameter stack_width=8; parameter stack_height=8; parameter stack_ptr_width=3; output stack_full; /stack full flag output stack_empty; /stack empty flag output stack_ptr_width-1:0 read_ptr; /read data address output stack_ptr_width-1:0 write_ptr; /write data address inp

49、ut write_to_stack;/write data to stack input read_from_stack; /read data from stack input clk; input rst; reg stack_ptr_width-1:0 read_ptr; reg stack_ptr_width-1:0 write_ptr; reg stack_ptr_width:0 ptr_gap; reg stack_width-1:0 Data_out; reg stack_width-1:0 stackstack_height-1:0;,8/2/2020,37,Microelec

50、tronics School Xidian University,/stack status signal assign stack_full=(ptr_gap=stack_height); assign stack_empty=(ptr_gap=0); always(posedge clk or posedge rst) begin if(rst) begin Data_out=0; read_ptr=0; write_ptr=0; ptr_gap=0; end else if(write_to_stack end,8/2/2020,38,Microelectronics School Xi

51、dian University,else if(write_to_stack end end endmodule,8/2/2020,39,Microelectronics School Xidian University,module FIFO_tb; reg clk, rst; reg 7:0Data_in; reg write_to_stack, read_from_stack; wire 7:0 Data_out; FIFO_buffer U1(.clk(clk),.rst(rst),.write_to_stack(write_to_stack), .read_from_stack(re

52、ad_from_stack),.Data_in(Data_in), .Data_out(Data_out); initial begin clk=0; rst=1; Data_in=0; write_to_stack=1; read_from_stack=0; #5 rst=0; #155 write_to_stack=0; read_from_stack=1; end always #10 clk=clk; initial begin repeat(7) #20 Data_in=Data_in+1; end endmodule,6.2.7 鍵盤掃描和編碼器,鍵盤掃描和編碼器用于在擁有鍵盤的數(shù)

53、字系統(tǒng)中手工輸入數(shù)據(jù)，通過檢測按鍵是否按下，產(chǎn)生一個唯一對應(yīng)此按鍵的掃描碼。 例：用Verilog HDL設(shè)計十六進(jìn)制鍵盤電路的鍵盤掃描和編碼器,8/2/2020,40,Microelectronics School Xidian University,控制信號狀態(tài)機(jī)轉(zhuǎn)移圖如下圖所示。 此時行列線的交叉處就 是按鍵的位置。根據(jù)已 確定的按鍵的位置輸出 其對應(yīng)的編碼信息。 其鍵盤編碼表如右表所 示。,8/2/2020,41,Microelectronics School Xidian University,為了使測試更接近于真實(shí)的物理環(huán)境，測試平臺中必須包括模擬按鍵狀態(tài)的信號發(fā)生器，能確認(rèn)按鍵對

54、應(yīng)行線的模塊Row_Signal和被測試模塊Hex_Keypad_Grayhill_072。模擬按鍵狀態(tài)的信號發(fā)生器可以嵌入在測試平臺中，通過不斷地給key信號賦值，模擬產(chǎn)生不同的按鍵信號。Row_Signal模塊用于檢測按鍵的有效性并確定按鍵所處的行。而Synchronizer模塊通過檢測各個行線值的或來確定是否有按鍵按下，當(dāng)此模塊的輸出發(fā)生變化時，被測模塊Hex_Keypad_Grayhill_072將會確定按鍵的位置并輸出相應(yīng)的代碼。,8/2/2020,42,Microelectronics School Xidian University,其Verilog HDL程序代碼是： / 頂層

55、模塊： module keypad(clock,reset,row,code,vaild,col); input clock,reset; input 3:0 row; output 3:0 code; output vaild; output 3:0 col; wire s_row;,8/2/2020,43,Microelectronics School Xidian University,hex_keypad_grayhill U1(.code(code),.col(col),.valid(valid), .row(row),.s_row(s_row),.clock(clock), .re

56、set(reset); synchronizer U2(.s_row(s_row),.row(row),.clock(clock),.reset(reset); endmodule /編碼模塊： module hex_keypad_grayhill(code,col,valid,row,s_row,clock,reset); output3:0 code; outputvalid; output3:0 col; input3:0 row; input s_row; input clock,reset; reg3:0 col; reg3:0 code; reg 5:0 state,next_st

57、ate; parameter s_0=6b000001,s_1=6b000010,s_2=6b000100; parameter s_3=6b001000,s_4=6b010000,s_5=6b100000; assign valid=(state=s_1)|(state=s_2)|(state=s_3)|(state=s_4) ,8/2/2020,44,Microelectronics School Xidian University,always(row or col) case(row,col) 8b0001_0001: code=0; /0 8b0001_0010: code=1; /